05-19-2010 08:05 AM
I am using a FPGA target in my cRIO , In my application the host VI runs with LabView Windows and related FPGA VI on cRIO. is there any way to make FPGA VI run automatically when I start the host VI? if I am not mistaking in RT Labview this feature is already available when the host VI is deploied. Thanks for the help.
05-19-2010 08:09 AM - edited 05-19-2010 08:10 AM
Startup VIs vs Startup Executables on a Real-Time Operating System
05-19-2010 09:17 AM
05-19-2010 09:23 AM
Totally agree with Adnan, this is the preferred method.
Also if you decide to create an executable for your RT Part, interfacing the FPGA.vi from there causes the bifile to be included in the executable.
Then you simply need to create a kind of start routine in your RT and an Start command in your host vi.
Christian
05-19-2010 03:59 PM
Thanks all for the replies, I tried Adnan solusion since it looked easier, however still the FPGA vi does not start to run automatically when the host VI runs, I added "Run invok node' before the while loop, the attached shows the snap shot of what I got, the right part of the picture shows my Windows block diagram VI and the left is FPGA front panel.
05-20-2010 02:12 AM
How do you check if its running?
Also be carefull, because when opening the reference to the FPGA.vi you can also select to "Open and Run" or only "Open", so the Run Method is not necessarily needed.
Christian
05-24-2010 08:36 AM
Hi Christian,
Do you mean the " Run the FPGA VI" option in Config. fpga VI ref.? please see the attached.
I leave the fpga front panel open while the host VI runs and check if it is runing or not.
05-25-2010 09:12 AM
Hi Shimbloo,
You can download the FPGA bitfile to flash from inside of your project explorer window by right clicking on the FPGA Target and going to RIO device setup and selecting your file.
Hope this helps.
05-25-2010 10:17 AM
The FPGA VI was runing automatically all the time when host VI was runing, in fact I was fooled checking the FPGA VI state by looking at its front panel, Christian's question triggered more investigation to see if FPGA is realy runing or not, since the FPGA vi block diagram runs on the target and Front panel on host PC, it does not show the common indication of runing state as Labview VI does, adding a boolean indicatore helps.
Thanks for the help.