I am working on programming a PXIe-7976R FlexRIO using LabVIEW 2017 and need help configuring the Xilinx DDS Compiler 6.0. I searched for examples and all I came up with was a document by Xilinx explaining how the IP works. Using the information, I tried to configure the IP, but I am not getting a signal out. One of the configurations I tried, involved setting the clock signal name under the "Clock and Enabled Signals" dialog as "aclk", but I get a warning at the bottom. If change the clock signal name from "aclk" to "No Clock", I get a terminal requesting a clock and I do not know how to proceed after that.
Is there a setting or step that I am missing? Is there an example that I can look at? Any tips?
Any help is appreciated.
Sounds cool, what is the application and what are you trying to achieve?
I provide these recommendations based on what I remember so I might have missed something. When configuring DDS compiler core with the new AXI interface you have four tabs (?), Configuration, Implementation and Detailed Implementation and finally a Summary, correct?
System Requirements – select system clock rate, # channels etc.
Parameter Selection – I used Hardware parameters pretty much all the time, allow you to select phase width and output width.
Phase Increment Programmability – if you would like to change phase increment (frequency), I used streaming to get the most flexibility, consume more resources though
Phase Offset Programmability – offset, I used streaming to get the most flexibility, consume more resources though
Output – what to output, I used Since and Cosine
Polarity – never changed
Amplitude Mode – Unit Circle
Implementation Options – memory AUTO, optimization AUTO, DSP48 use MINIMAL
Detailed Implementation Tab
AXI Channel Options TLAST – not required
TUSER Options – Input – not required
Latency – Auto
Control Signals – ACLKEN and ARESETn
Thank you for the information. I am trying to implement the Costas Loop PLL for the purpose of tracking the phase and frequency variations acquired by the PXIe-5646R. The input signal will be a signal modulated with the BPSK or the FSK scheme. For now, all I have to do is generate the sine and cosines.
I configured the IP using your recommendations, but my questions come from Page 2 of the configuration dialog, the Clock and Enable Signals. In addition, I am not sure how to wire the rising edge clock terminal (aclk) in the block.
Assign the 'clock signal name' a value of 'aclk'. You'll get a warning about sequential execution giving inconsistent results without a clock enable, but you can ignore that if you intend to leave dds core free running and insert logic downstream of the core that's capable of ignoring any data that comes out of the dds core until everything gets initialized.