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Why would these FPGA builds not have the green box around them after successfully compiling?

I don't get it. I create a build spec of the FPGA file, and then I build it. It says it compiled successfully. But when I try to run in from my RT controller, I get an error.

 

I noticed it's only happening to the ones that don't go green, but....like I said I compiled it. And when I right click and say to build again, it says the bitfile is up to date....

FPGA error.PNG

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I can't find a reference but I always thought the green box sets the default build specification. Do you have more than one build specification per VI?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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That’s supposed to indicate if the according rt executable is configured to “run on startup”.after you deploy it.

Rolf Kalbermatter
My Blog
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Was responding from my mobile and there things look sometimes difficult to see in context. For the FPGA build it means that the according bitfile has been generated and there should be no material modifications to the source code for them that would cause altered code generation. This last point can sometimes be a little finicky in my experience. While cosmetic changes to the VIs for the FPGA bitfile usually have no influence on this status, LabVIEW sometimes can consider modifications to VIs that should have no material effect as requiring the regeneration of the bitfile.

Rolf Kalbermatter
My Blog
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I do a lot of FPGA work and am not familiar with this green box at all.....

 

If it's as Rolf suggests that it indicates an up-to-date Bitfile, be aware that conditional disable structures can play havoc with this. Having multiple versions of code with minor changes in code will result in all Bitfiles becoming obsolete once the conditional compile is altered.

 

There have also been enough cases where I've compiled something, not touched the PC at all in the process and LV still maintains that the bitfile and the source code do not match. There are clearly conditions where LabVIEW just gets confused.

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I'm with Terry on this one. The green box shows the default build specification per VI. I don't think you can tell by this box whether the bitfile is supposed to be up-to-date.

You can right-click a build specification without the box and select "Set as default", then the green box will move from the current default build spec to the selected one.

 

To the OP:

How do you call the bitfile from the RT code?

In the "Configure Open FPGA VI Reference" dialog you can choose between build specification, VI, or bitfile. When set to VI it will use the default build spec bitfile.

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