While loop timing control does not work

[incasekim]

Hi, 

I am currently running a co-simulation using multisim.

 I don't know how this happened, but the while loop timing control in my FPGA file stopped working all the sudden. 

I set the control_dT as 1200 as can be seen in the attached picture, but the output dT comes out as 40000. I also get the same way too high output no matter what kind of values I put in. 

I've not changed anything in terms of control, and same thing happens for other FPGA files. 

Is it possible that I accidently changed some settings???? 

[Terry_ALE]

Which of the two loops stop?  If you are running the FPGA VI in simulation mode you could probe it or even use sampling probes.

[altenbach]

How long does it take to execute the contents of the loop? You cannot go faster than that. What does the subVI do? What hardware is this running on?