What will cause IO Module IO Enabled to not come up

[JKneale]

I have been experimenting with the example program  for "NI 6583 Continuous Generation - Internal Clock".  The "IO Module IO Enabled" signal is never coming up, and so the code is stuck at the beginning sequence block.  "IO Module\DCM Locked" comes up, so the CLIP clocking resource is locked

I am using a PXIe-7961R and an NI-6583.  I've moved the IO module CLIP to the project directory to play with it, and tried to recover things back to normal, but unfortunately also modified the example program as installed in the original location.  Everything builds fine.  Running another untouched example program using Connector CLIP for the NI 6583 works fine, so my hardware is connected correctly.  The IO Module Properties general tab shows the correct path

I know I can re-install off distribution media to get back to normal, but want to understand what I did wrong.  What are the things that are necessary for the "IO Module IO enabled" pin to come up, assuming that the hardware is physically connected and the code builds?

[James_Battleaxe]

Hi,

There shouldn't be anything extra you'd have to do for the IO Enabled boolean to turn on. It should be all part of the CLIP and you just need to drag it onto the FPGA block diagram. Could you post some screenshots of your project explorer window or the project itself? That could provide some more clues on what's causing this odd behavior.

[JKneale]

Unfortunately I've already restored the CLIP and project files to the as-shipped configuration and gotten it working again.  I originally made some CLIP changes within the installation directory, then moved it to the project directory per http://zone.ni.com/reference/en-XX/help/372614J-01/frioamshelp/adding_fam_clip_to_lvproj/ and made changes there as well.  The project may have been pointing to files in both locations and became a tangled mess.

My original problem is fixed, and I learned to be more careful to configure my CLIP location before introducing it to a project.  I was just curious in general regarding the various things that would cause that signal not to come up.

[James_Battleaxe]

Hi,

Got it. I don't think the issue would be with how you moved the files between directories but more with the changes you made in the CLIP. Either the signal for IO Enabled didn't get passed from the CLIP to LabVIEW FPGA, or some logic involving the IO Enabled signal was altered. 

We have limited support on modifying CLIP files, but if you do run into this issue again, feel free to let us know and we can do our best to help out.