VHDL wrapper for HDL Node

[A.N.Other]

Hi everyone, I'm new to using the HDL Node and I'm having a few teething difficulties, mainly with the fact that LabVIEW forces all one-bit I/O signals to be std_logic_vector(0 DOWNTO 0). The IP I am trying to integrate uses std_logic for these signals so I need to add wrappers for this purpose. For the input signals, I have found that IP_name <= LV_name(0); works quite well but I have not been able to find an equivalent for the output signals.

Could someone who is more versed in VHDL than me suggest a way of seting a std_logic_vector(0 DOWNTO 0) to equal a std_logic signal?

Thanks,

Andy

[Philip.k]

Hello Andy,

Rather then using a HDL node try using this as it is a more comprehensive means of accessing third party IP and does not require creating a wrapper.

http://decibel.ni.com/content/docs/DOC-5907

Regards,

Phil

[A.N.Other]

I'm afraid I'm using LabVIEW 8.6 so I can't use the IP Integration Node, hence the need for the wrapper.

Thanks,

Andy