10-05-2018 04:12 AM - edited 10-05-2018 04:18 AM
Hi all,
I have written a VHDL program and compiled(Synthesized) and simulated with Vivado environment. I imported that into LabVIEW environment through IP integration node, it imported successfully.
When we are compiling that code on LabVIEW that and trying to download that program into cRIO module, Xilinx compiler is compiling and terminating process with error.
The errors are something like that:
LabVIEW FPGA: The compilation failed due to a Xilinx error.
Details:
ERROR: [Synth 8-691] width mismatch in association of array element 0; element has 8 bits, expression has 1 bits [E:/NIFPGA/jobs/i1d8ERJ_jW16D67/command_builder_C17_VHDL.vhd:99]
ERROR: [Synth 8-691] width mismatch in association of array element 1; element has 8 bits, expression has 1 bits [E:/NIFPGA/jobs/i1d8ERJ_jW16D67/command_builder_C17_VHDL.vhd:99]
Now the error is completely not telling why it is there, and where it is in the code. I am getting hundreds of such lines of errors.
What may be the possible problem?
Cheers
Tahir
10-08-2018 06:23 AM
Hi,
Been a while since I did something VHDL related (applies to LabVIEW in general I am afraid) but I would guess it is related to data mismatch.
Information about supported data types when using CLIP or IP Integration node.
http://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/integrating_hdl/
Boolean --> std_logic
U8 / I8 --> std_logic_vector(7 downto 0)
U16 / I17 --> std_logic_vector(15 downto 0)
U32 / I32 --> std_logic_vector(31 downto 0)
U64 / I64 --> std_logic_vector(63 downto 0)
FXP --> std_logic_vector(x downto 0) where x is in range [0,63]
...
Have you checked that the data you expose in the IP integration node is compliant with LabVIEW data types?