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Using DMAs with Ethernet RIO

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Amongst other things, we want to measure six staggered PWM signals to ensure that their staggering is actually being evenly distributed in the way we intended. We were thinking the best solution might be to grab an NI 9147 Ethernet RIO and a couple of NI 9381 multifunction I/O modules. That gives us all the I/O we need with some flexibility in the future between the extra I/O on these modules and the extra slots in the RIO. For our application, we seem to have sufficient sampling rates with the hardware, but we don't think the Scan Engine will be sufficient to get the PWM signal profiles we are trying to capture. Although we have worked with cRIOs in the past, we haven't utilized the Ethernet RIO yet, so we've been doing a little research:

  1. This link appears to confirm that "The chassis can be added as a stand-alone target to a Windows-based system" and we can in fact re-program the 9147's FPGA: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YGx7CAG&l=en-US
  2. From this link, it appears we do actually have 16 DMA FIFO channels on the 9147 (which we should have access to when reprogramming the FPGA): https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P9ZVSA0&l=en-US
  3. The context of this last link regarding the Ethernet and EtherCAT based RIO systems seems to imply in the API section that we can "use the LabVIEW FPGA Host Interface API" on this system "to perform functions such as reading and writing to registers, and DMA transfers." https://www.ni.com/en-us/shop/compactrio/expansion-i-o-for-labview-rio-systems--an-in-depth-comparis...
Putting this all together, it seems like we would be able to reprogram the FPGA to use the DMA and access that from our Windows host application. Can anyone confirm that we are understanding this correctly or clarify where our thinking is off?
William Griffin
NI Certified LabVIEW Architect
NI Certified Professional Instructor
DISTek Integration, Inc. - NI Certified Alliance Partner
http://ww2.distek.com
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Accepted by topic author William_Griffin

Putting this all together, it seems like we would be able to reprogram the FPGA to use the DMA and access that from our Windows host application. Can anyone confirm that we are understanding this correctly or clarify where our thinking is off?

Yes, you can. The KB Can I Access My FPGA Target from LabVIEW 64-bit? shows an example of how you can bypass the cRIO controller and communicate with the FPGA directly from the Windows host application. As a matter of fact, when we debug and click the Run button on the FPGA VI, we are interfacing with the compiled FPGA VI from the Windows host LabVIEW ADE directly.

However, the latency of communicating from a Windows host via Ethernet is definitely much higher from the real-time controller but depends on the application, the latency might not matter at all.

 

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