Using CLIP with array data problem

[fanwel]

Hai all,

I need helps from anyone here. I have a vhdl code that I used a declaration of a package because some of my input data is an array. Below is the short code:

library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use ieee.numeric_std.all;

package MDWT_PKG is
  type vector is array (natural range <>) of std_logic_vector(7 downto 0);

end MDWT_PKG;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library work;
use work.MDWT_PKG.all;

entity dwt1d is
	port(
		   clk : in std_logic;
			rst : in std_logic;
			dwti : in std_logic_vector(7 downto 0);
			idv : in std_logic;
			
			odv : out std_logic;
			dwto_L : out vector(3 downto 0);
			dwto_H : out vector(3 downto 0);
			
			ramwaddro : out std_logic_vector(5 downto 0);
			ramdatai : out std_logic_vector(7 downto 0);
			ramwe : out std_logic;
			wmemsel : out std_logic
			);

end dwt1d;

 The codes are successfully compiled and simulated in ISE and Modelsim. After that, I import the .vhd file in Labview using CLIP. However when I check the syntax, the compiler said an error, which is the dwto_L : vector is unsupported data type. Why this error occurred? Even I have declare the vector type in the pacakge. Is it have any steps to use a package in CLIP? Hope anyone can helps..thanks inadvance