User Defined Refnum Error

[David_L]

Don't know what happened with that link, but the document that was mentioned earlier is here:

http://digital.ni.com/public.nsf/allkb/43D6024A5307137D862576B1007C20FD?OpenDocument 

[dskrabacz]

Hi,

I am dealing with the CompactRIO 9074 and I have connected the 9870 up to this chassis. I am using the example virtual instrument that was recommended from James. I was able to input all of my Read_FIFO and Write_FIFO with my specific ports, and have modified the ports. When I run the FPGA program, it initializes to step 7, and then exits with the following error message: "Too many DMA channels have been requested or some requested are conflicting. The current target has 3 DMA channels." Does anyone have a fix for this? Thanks.

-Daniel Skrabacz

[dskrabacz]

Hi,

I am dealing with the CompactRIO 9074 and I have connected the 9870 up to this chassis. I am using the example virtual instrument that was recommended from James. I was able to input all of my Read_FIFO and Write_FIFO with my specific ports, and have modified the ports. When I run the FPGA program, it initializes to step 7, and then exits with the following error message: "Too many DMA channels have been requested or some requested are conflicting. The current target has 3 DMA channels." Does anyone have a fix for this? Thanks.

-Daniel Skrabacz

[charris]

Daniel:

The cRIO only has 3 DMA channels for communication between the backplane and the controller. A FIFO will occupy one DMA channel, so if there are more than 3 FIFOs, you'll get the error you're seeing.

Your best options are probably going to be:

- Offload processing from the RT controller to the FPGA (to eliminate the need to send time-critical data to the controller over a FIFO) and eliminate a FIFO.

- Combine data from multiple sources and send it across one FIFO (you can parse it out using a "Decimate 1D Array" function on your RT host).