Use USB 6221 board for implementing a serial interface master

[PaulieQ]

Hi,

I want to implement in LabView the master for a common serial interface using USB 6221. The master generates a CLOCK signal and receives from slave the signals. One frame looks like

                                                                     FRAME 1                                                                                FRAME 2 ......

              _   _   _   _   _   _   _   _   _   _   _   _   _   _     __________     _      _

Clock (Master) |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|        |_| |_|

                                            ____                  ________         ____         _________                __________         ____

Data (Slave)    _____|   |_______|       |___|   |___|       |_______|        |___|   |

The communication works (I've already tried it with master in FPGA).

In LabView I did the following (you can also see it in the attachment):

1. Use Frequency Out to generate a clock 500kHz. Signal -> FreqOut

2. Drive the Frequency Out as Clock Source for Counter 0  to generate Impulses. 10 pulse up and 40 pulses down. A frame has 40 pulses. 10 pulses between frames. Signal -> PFI7

3. Using an external hardware circuitry: CLOCK-Master = FreqOut NAND PFI7 (this is the signal like in diagram above). NAND is a gate/electronic component.

4. Drive the Data (Slave) line to a Digital Input (port 0.x) and read the values using the Clock Source (FreqOut / CLOCK-Master - I've tried with both of them).

(I know that I can generate the Clock using a Digital Output from port 0.x. but the one used as DI at 4. is the only DIO which is not used from my board).

The problem is that the Data read from the Digital Input is not synchronized. If I read the values continuously from 50 frames in one or two some bits are missing. For test purpose the slave sends always the same data. And once instead of 11110000 (4x1, 4x0) the software reads 1110000 (3x1, 5x0).

I don't think it's a delay (line delay) or a setup time problem . I tried using different edges for Digital Input Read (falling=fallend and also rising = steigend) and I see the same behavior. As long as I'm using the same cable length it should be ok. And 500 kHz is not a high frequency. Using FPGA, with the same set-up I reached 4-5 MHz.

In the Datasheet for USB 6221 it is said that the clock for Digital Input is 0 to 1 MHz. So it should work just fine.

 

Regards,

Paul