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USRP RIO FPGA Compilation Error

I am getting the following error when I compile my design for USRP 294x 

I am using LabVIEW 2020 f1 32 bit with USRP 21.0.2

The error randomly appears on each compile and sometimes if I create a new build spec, it works fine for a few compiles and then randomly appears again. 

 

***************************************

 

LabVIEW FPGA: The compilation failed due to a Xilinx error.

Details:
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/Kh65wgl_X6Plm2i/NiFpgaUltraRamFifo.vhd:50]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:15 . Memory (MB): peak = 941.781 ; gain = 326.875
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
4 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace {C:/NIFPGA/jobs/Kh65wgl_X6Plm2i/.Xil/Vivado-2352-LAPTOP-JISTQGKE/realtime\UsrpRioTop.tcl}"
invoked from within
"synth_design -keep_equivalent_registers -top "UsrpRioTop" -part "xc7k410tffg900-2" -flatten_hierarchy "full""
(file "C:/NIFPGA/jobs/Kh65wgl_X6Plm2i/synthesize.tcl" line 83)
invoked from within
"source "C:/NIFPGA/jobs/Kh65wgl_X6Plm2i/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Sat Jul 9 15:09:08 2022...

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What does your design do? Without context it is really difficult to help you out.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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I am using USRP RIO to receive GSM downlink signals. So, the signal from the DDC is passed through further signal processing on FPGA. I am using about 50% resource on FPGA. 

But, my guess is that the error is not related to my FPGA IP, since that would have caused it to fail or generate an error each time, isn't that the case?

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Any thoughts? 

One thing I would like to point out is that the Error says:

ERROR: [Synth 8-5809] Error generated from encrypted envelope. [C:/NIFPGA/jobs/Kh65wgl_X6Plm2i/NiFpgaUltraRamFifo.vhd:50

 

while as I understand, there is no UltraRAM in USRP2945. 

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I try to solve these errors indirectly. For example I comment our certain parts. The xilinx report can be a bit of a rabbit hole.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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