Typical time an interrupt request takes between LV RT and LV FPGA.

[Michel_Gauvin]

I currently don't have the hardware to test this and I've been looking around for some timing statistic about the time it takes for an interrupt request to be processed between LV RT and LV FPGA ( LV RT generate interrupt request, LV RT wait on ack, LV FPGA get interupt request, and LV FPGA ack, LV RT continue).  I know that the interrupt request has higher priority than timed loop on LV RT, and for the sake of this question let say that the LV FPGA does not perform anything in between the reception of the interrupt request and the ack.

Anyone has any timing?

[Queen_Nadine · Accepted solution]

Hello Michel_Gauvin,

I found the following KnowledgeBase article that may answer your questions:

LabVIEW Real-Time Module Benchmarks for LabVIEW FPGA Module Applications

I hope this helps!

Regards,