Total slice change with compilation

[Paolo_Squillari]

Does anybody knows why compiling an FPGA VI twice, with no change, the total slice change?

I've done this test:

1. realized a new FPGA VI
2. first compilation => total slice: 42.6%
3. second compilation => total slice: 44.8%

Thank you,

Paolo.

[Dragis · Accepted solution]

The Xilinx tools, by default, will only optimize things enough to make the design meet all the requirements. In addition, some of the later tools throw in some randomization to search for different (and possibly better) designs. These two together can cause designs that aren't fully utilized to swing quite a bit in slice count, timing, etc.