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Timing errors in SCTL code

Hello, I'm just now learning about efficient coding in FPGA and I've run into a wall.

 

I'm trying to implement code in a SCTL where each input element (real and imaginary components) is 1) scaled by a complex coefficient c, 2) the difference is found with respect to a reference value, and 3) the squared L2 norm of the difference is computed. The input vector is split into 2 pieces and processed element-wise in parallel. To achieve the required accuracy, I need around 32 bits precision (note: all values are [-1,1] which is why I've limited the word and integer length for all operations). 

 

My problem is that the code (attached) produces timing violations and exceeds the SCTL limit of 25 ns. I've tested for 20 bit word lengths (which is just at the accuracy limit) and still have timing errors. I know I could implement pipelining  but this would delay my result at least 1 cycle which would mean that the computation of the coefficients c would start accumulating (big picture: for many different input vectors, the coefficient c is computed and fed into this code as a scaling coefficient, the output of this code is the norm(error)^2. ).

 

Is there any possible way for this code to be executed in one cycle without pipelining? And, if not, is it better coding practice to pipeline or to slow down the clock of the SCTL? 

Thank you for any help you can provide!

Screenshot 2022-04-05 at 16.05.48.png

 

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Hi akarpilow,

 


@akarpilow wrote:

Is there any possible way for this code to be executed in one cycle without pipelining? And, if not, is it better coding practice to pipeline or to slow down the clock of the SCTL? 


Well, the usual recommendation is to use pipelining!

Not all code will fit within the "1 clock cycle" of your SCTL, so you need to provide means to run things in parallel - by pipelining…

Do you need the SCTL at all? Can't you use a default FOR loop?

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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