Synchronizing and polling Boolean TTL pulses in separate FPGA VIs

[Seiji_ANU]

Hi guys, wondering if anyone can help me with a timing/synchronization problem.

In a nutshell, I have two FPGA cards, which I write to from a top level VI. I create a TTL pulse on one FPGA and I need the other FPGA VI to be able trigger off this. Right now I am polling a Boolean.

Specifically:

FPGA card 1 has two parallel loops: the control loop, and the pulse loop. In the pulse loop, I create digital pulses (TTLs) on the order of 500us period with a 40% duty cycle.

In the control loop, I am running a PID controller, but that`s irrelevant to my query. What is relevant is that depending on the TTL being On or Off, my PID will behave in a certain way. Now in the control loop, I access a local variable of the Pulse on/off Boolean coming from the Pulse loop. I have this wired up to output another TTL pulse in the control loop, to test if it`s working. It is, and I can compare pulses on an external oscilloscope. There`s maybe a 1us delay, which I can live with, and the two TTLs from the VI are in sync.

My problem is, how can I efficiently mimic the behavior in a separate control loop, in a separate VI running on a separate FPGA card?

For now, the VI on FPGA card 2 simply has a control loop that is polling a Boolean in order to trigger some different cases in a case structure.

I have tried using a FIFO write on FPGA card1 Pulse loop, but cannot work out how to read this efficiently in my control loop on FPGA card 2.

What I have tried is to Invoke the Method on a top level VI of the FPGA card 1 FIFO, invoke this as read, then pass the data to a second FIFO that is fed in the reference from FPGA card 2. This is in the Write method. And in the VI on FPGA card 2, I create a FIFO that reads in and outputs a Boolean.

My problem is that whenever I run the top level VI, only one FPGA VI will run at a time (I`m monitoring the respective loop counts). Interestingly, each time I click Run, the other FPGA card vi will run, and they alternate (one loop counter will run, while the other will be at 0, so not even starting).

I have two questions for anyone who was kind enough to follow my long explanation above:

1) Is there a better way to pass a Boolean which is being polled on a separate FPGA vi?

2) If the FIFO method is the way to go, have I done something silly?

I might not have given you enough information, so please ask if I have omitted something important.

Some details: I can accept up to around a 5us delay between the pulse ON/OFF stages that reaches the second FPGA VI.
I tried using a Read/Write Control in the top level to poll the Pulse On/OFF Boolean, but this took around 800us so was not useful for what I want to do.

I have attached screen shots of a stripped down version of my code, if that helps.

Thanks!

[BillMe]

Which type of FPGA card are you using? If it's PXI, then you can use the backplane trigger line(s) to synchronize your FPGA cards. There's a good example under "R Series", "Device Specific", "RIO Master-Slave".

[Seiji_ANU]

G'day BillMe,

Thanks for the reply, I'm using two PXI-7853Rs. I'll check the example that you suggested, much appreciated!

Seiji