Sync betwwen SCTLs

[Cobmetal]

HI ,

Im using FlexRio Kintex 7 and 6585B adapter .

I have few SCTL which running under the same clock.

from the host im loading data to the DRAM and from the DRAM im sending data using a protocol which is implemented on the TARGET.

How i can synchronize between the SCTLs that all the data will sent simultaneously .

im using a boolean variable for a case structure inside each SCTL , which points to send/not send data . How I can control these Boolean Variables simultaneously , (each variable is in SCTL) ?

Thank You .

[Cobmetal]

Someone ?

[Case_in_Point]

Hi Cobmetal,

Could you elaborate more on what exactly your architecture is doing? I think you're saying you have multiple timed loops, on the same clock, that need to all toggle a boolean to start outputting data. You want them to all toggle at the same time. What controls when they all need to toggle and start outputting?Also, I'm not sure where the DRAM is coming in to play; I hope you aren't trying to read the same data from the DRAM in multiple places, because I do not think that will work. DRAM access has to queue up read and write requests, so if you had each loop request to read from DRAM I'm pretty sure there is no way for them all to get data at the same time.

It sounds like you would have a much easier time if you only used one loop, if all of the loops are running off of the same clock. What's the justification for splitting them up into multiple loops? In general, the normal mechanisms to communicate between different loops would be things like writing to memory or using variables to communicate between them. But these tools are really meant for crossing clock domains, which you don't need to do. 

Cason

NI Applications Engineer

[Cobmetal]

Using the FlexRio , im simulating few optical devices.

I have a recorded data from a real sensors , this data is loaded to the DRAM --> FIFO and then sent out using a communication protocol. The data of each simulated device has its own size and length . when the loading is finshed to the FIFO , it stats send out the data immediatley . for each device i built a state machine for all the process , each one have a "select" when it goes high the data is sent out. what i need is that all the "selects" will toggle at the same time.

Im not trying to read the same data from the DRAM in multiple places , each simulated device has its own DRAM and data.

[Case_in_Point]

Alright, in that case you could probably replace these Select booleans in each of your loops with global variable reads. I suggest global variable because local variables on FPGA always have to bring along a front panel element. Global variables do not. So in whatever loop is controlling all of the simulated devices' loops, it'll write True to the global variable, and all of the other loops just read from this global variable. Since they're all tied to the same clock, they'll all see the variable go to True in the same tick and start their generation.

[Cobmetal]

I've tried your suggestion with an additional modification , i've used local variables ( six variable ) , and put all of them to a AND gate , and the output of the AND gate is the trigger . i've put the AND operation inside another SCTL ( with the same clock domain ) , and during the compilation i have an error that tells me to replace this SCTL with a While loop , i've replaced it and the compilation finished successfully . My question is how the While loop will impact on the performance ?

[Case_in_Point]

I think I've completely lost what you're trying to do here. It sounded earlier like you had one source of logic that was supposed to trigger a bunch of other parallel loops to start writing data to memory, right? As in, loop 0 has some logic in it, and when that's true loops 1-6 are all supposed to write data.

But now you've talked about using a bunch of variables together with an AND gate? So when all six loop variables are True, you'll get a True out of the AND gate? This sounds like exactly the opposite; instead of one loop controlling six others, you have six loops that all control the one. As to the specific error, you'll have to provide more detail on that error if you want some further help understanding it, but I think the better option is to step back and make sure you have a clear understanding of the overall logic. 

And just for information's sake, having a While loop instead of a SCTL will mean that loop will run non-deterministically, so you have no idea how long it will take to process. That's probably not good if this loop is running some triggering logic, which sounds like the case. But I'm not even sure exactly what you're trying to accomplish here.

Regards,

Cason

NI Applications Engr.

[Cobmetal]

Hi 

ill try to expalin myself better.

i have 6 sctl which are running on the same time domain. Each sctl has a state machine inside. In each sctl im loading a binary file into the DRAM and when the file is loaded i have a trigger to next state , this state is taking the data from the DRAM and is sending it using a unique protocol to an external device. Because of the different file size each file has its time that takes it to load it to the DRAM , and the result is that all the sctl send the data outside in different times , what i need to achieve is that all the sctls will start to send data at the same time (synchronousally). 

[SpaceFlight]

You could try using an occurrence. 

Have the SCTL that takes the longest time to load set the occurrence and then all other loops would wait on the occurrence and start when the occurrence is received.

 

[Cobmetal]

I dont know for sure which load takes the longest period.