Speeding up FPGA code

[Jack_W]

Dear all,

I have a pretty "urgent" problem here:

I wrote a FPGA code, that I tested for a loop rate of 1kHz successfully before an important lab week. Now, I found out that I need to increase to sampling rate up to 5kHz, however, I notice that my FPGA code cannot execute that fast.

As I am not that experiences in FPGA, can anyone give a hint on how to speed up the code?

Thank you all.

[GerdW]

Hi Jack,

you could start by setting a different Loop time ("count(µsec)" control) to change the loop iteration time…

Do your measurement modules support the higher sample rate?

[Jack_W]

Hi,

thanks for your reply.

I want to have the loop time flexible, and I note (when I check the actual loop time), that around 3kHz is the fastest the loop can run. When I request 3kHz, the actual rate is 3kHz. When I request 4kHz, the actual rate is 3,xx kHz.

The modules Do support higher sampling rates.

Cheers JP

[Naveensoliton]

Hi Jack, 

 You can try parallelise code blocks as much as possible without affecting sync. Also, I see that you are writing to a FIFO named "daten". What is the configuration that you are using for this FIFO. What is the LabVIEW version of the code? If you can give me the details, I can help you make the code faster. It will be easy to help if you can upload a non broken code with a dummy project.

Regarda,

Naveen

[D.Barr]

Recently NI support sent me the following link. It explains tricks to improve FPGA executions speed and/or reduce FPGA foot print. It well worth a read:

http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816

Hope its helps

Dave B

[Jack_W]

Thanks for the reply,

I hope the file attached helps. It is labview 2013 - I just increased the DMA Depth to 5000 (from 1024), because I thought this might be the problem - it was not - so that can be ignored.

The project is a bit messy, by the fpga code is the one under the first chassie, named "fpga_code.vi'.

One idea of mine is:

could I send the data from the time critial loop via a target scope fifo to another loop, where I than finally send the target-to-hos FIFO?

Thanks

[Naveensoliton]

Is the "looptime" indicator in the bottom loop used in any logic in your host code ? Or you use it just to measure the speed?

[Jack_W]

it was just to check whether the loop reaches the speed I need

[Naveensoliton]

Can you please try the below change and let me know if it works... I have just placed the Write FIFO loop in parallel

[crossrulz]

Can you show the code where you set the loop rate on the host (RT) side?  I suspect an issue there.  Everything else I can find should only add up to around 3us for the loop rate, but you are trying for more like 200us.