Simulating FIR Compiler 7.2 in Interpolation Mode

[tcapuano-aps]

Hi,

Has anyone been able to simulate the FIR Compiler 7.2 in Interpolation Mode?

I have a been able to confirm Single Rate and Decimation. According to the Sampling probe, it appears that the node rapidly, requests 16 samples from the upstream FIFO and then sits idle. The 16 samples match the Input FIFO default size in the 7.2 Guide. It also looks to output 1 value.

My setup is a DMA to the IP using the 4W-AXIS conversion and then AXIS-4W Conversion to another DMA. This works fine with Decimation and Single Rate.

Regards,

Tom