SbRIO 9651 external clock

[OmarKhaledAli]

How can I use a DIO pin on SBRIO as an input clock to my SCTL in a LabVIEW FPGA code? Please provide example for this as I can't understand this part from the LabVIEW FPGA module tutorial on ni website.

Noting that my external clock will be a 10 MHz clock and I want to read some data at the negative edge of this clock.

[jiangliang · Accepted solution]

yes you can, check the sbrio CLIP generator, you can generate a clock source here.

[OmarKhaledAli]

Hello,

Thank you for your answer, I have successfully created my external clock that I am going to use in the SCTL, however, I have a question regarding the SCTL, does the SCTL execute on the falling or the rising edge of its input clock?

if it is the rising edge, is it possible to make it executes at the falling edge of my external clock?

[OmarKhaledAli]

Thanks for your answer, I have successfully created the external clock that I am going to use as the clock of my SCTL in the labview FPGA code, however, I have a question, does the SCTL execute at the rising or the falling edge of the clock?

If it is at the rising edge is there any way that I can make it run at the falling edge of my external clock?

Thanks 

[jiangliang]

Well, that's something I would like to make sure, too😀

I assume it should execute at every rising edge, but I'm not sure, and I didn't find an easy way to validate this idea.

Maybe we can input a low-speed clock, say like 5MHz, and flip the DIO in SCTL, maybe we can get some information on this issue, but we also should consider the shift reg of the DIO output?

[OmarKhaledAli]

What do you mean by "flip the DIO"?

[OmarKhaledAli]

Also I have a work around that I think it may work, I thought about creating a new derived clock double the rate of the existing external clock (20 MHz) and do processing at the odd iterations of the SCTL (when i=1 means that it is the 2nd iteration of the SCTL so it is the 2nd positive edge of the 20 MHz clock and so it is the 1st negative edge of the 10 MHz original clock)

What do you think?

[jiangliang]

I think that should work; good idea!

Also, I think if we look into the sbrio clip generator's XDC file, we should be able to add some instruction about using rising or falling edge, I just don't know how, but for people who really develop FPGA for living it shouldn't be a problem.

Another idea: maybe we can ask CHATGPT for advice:)

[jiangliang]

According to chatgpt:

Yes, I'm familiar with LabVIEW FPGA. Regarding your question, by default, the single-cycle timed loop in LabVIEW FPGA is triggered on the rising edge of the clock that is specified as the loop clock. However, you can change this behavior by setting the "Timing" property of the loop.

To set the loop to trigger on the falling edge of the clock, you can follow these steps:

1. Right-click on the single-cycle timed loop and select "Properties" from the context menu.

2. In the "Properties" dialog box, select the "Timing" tab.

3. Under "Timing Source," select the clock that you want to use as the loop clock.

4. Under "Timing Type," select "Falling Edge."

5. Click "OK" to save the changes.

After you have made these changes, the single-cycle timed loop will be triggered on the falling edge of the specified clock instead of the rising edge.

Well, I'm not sure if this will work,since chatgpt is good at makeup answers.