Sample rate vs clock rate in cRIO

[Paul_Knight_Lockheed_Mart]

I trying to get my head around  the difference of sample rate vs clock rate in the cRIO so I can properly explain it to my optical engineers.

I have a FPGA code that is just the basic example with some IO.  Modules 1, 2, and 3 are NI-9201 with a sampling rate of 2uSecs.  The FPGA is running at 40 MHz or 25nSec/Cycle.  Reading in the documentation the While loop itself takes minimum of 3 clock cycles.  Estimating the other functions in the loop take about 7 clock cycles, the loop should execute in 250nSec.

This is faster than the NI-9201 can sample.

What does the FPGA do?  Does it wait for the sample to finish?  Does it take the value from the previous sample?  Do we get a partial sample?

[Sam_Sharp · Accepted solution]

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@Paul_Knight_Lockheed_Mart wrote:

Does it wait for the sample to finish?

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Yes - the loop will actually execute slower - it will wait at the I/O node until the sampling is complete - the time of which will be the sampling rate of whichever module is in the loop. For example, some of the high resolution analogue modules have very slow reading times (like 52ms) so the loop will run at a rate of approximately 52ms (depending on whatever other code you have in there). 

If you have some high-speed digital I/O, you would almost definitely want to put it in a different loop to any analogue I/O so it doesn't slow your loop down.

I think some modules are able to run in a single cycle timed loop - in this case, the module will execute in a single clock tick (e.g. 40Mhz).

[Paul_Knight_Lockheed_Mart]

Thanks

[Sam_Sharp]

Normally you would mark the post that actually answered your question as the solution, and give kudos to any other posts that were helpful, rather than mark your own 'Thanks' as the solution 🙂

[Paul_Knight_Lockheed_Mart]

Sam,

Sorry, I thought I did mark yours.  At least it looks like it from where the green solution box shows up in the website.

Paul