SERDES Clip Using Regional Clocks

[deadbug]

So I’m thinking I ought to be able to hook up the Strobe with the 100Mhz clock, then hook the data into one of the LVDS_IO lines and be able to get the data that way. I’m having a new problem though. I’ve hooked up a 100Mhz clock to the strobe but when I run the FPGA it just breaks and tells me... "An erro was detected in the communication between the host computer and FPGA target" I’m using the sample project found in the help. Specifcially "NI 6589 Finite Acquisition - External Clock Start Trigger (FPGA)" I don’t even get a chance to press commit before it errors out on me. The clocked process I think it is getting mad at is the one using the “IO Module\Acq_Regional_Clock” I having been looking at Figure 9 in the getting started guide for the 6589 module, and everything looks correct. I have a 100MHz LVDS clock hooked up on the strobe signal. And then from http://zone.ni.com/reference/en-XX/help/372614J-01/friohsdio/6589_serdeschan_clipref/ If I’m reading this right, as long as I choose bypass, the strobe should act as the SERDES clock for the LVDS input channels. The other ineteresting thing is the example project allows you to use an internal clock source for the regional clock. Even doing that I still end up with the same problem. It pretty much just looks like the regional clocks aren't working. Is there some enable I'm missing? What is preventing the example project from working? I can’t help but feeling I’m making this way harder than it needs to be… Thanks, Matt

[BdogTheWatchdog]

Hey Matt,

Have you tried running any of the other examples? I've also seen cases where this error appears and the FPGA code still 'works' - is this the case?

In the case that the examples don't work at all, it would boil down to either an issue with the setup, the hardware itself, or the machine/driver. Since you claim that the setup is fine per the Getting Started Guide, we can do the following:

• Test the device on another machine 
• If it does work on the other machine, or if we don't have another machine to test, provide a MAX technical report (of either both machines, or just the one if we don't have access to another) to document system specs.

Bdog

[deadbug]

I was able to get it to work ... but...

In order to do so I had to remove all of the controls and indicators out of the regional clock loop.  The only way I have found to get information to and from that loop is using FIFOs.  I think the issue is the back end interface LabVIEW has with the FPGA for those controls.  Even though it isn't suppose to be running yet because of the sequencer in there, it still blows it up because the clock isn't technically running yet.

Is this a bug, or am I still not doing something correctly?