Rising Integrator (Modulus function and Simulink model vs Labview VI)

[ESturov]

Hello, everyone.

Recently I came across one issue, that I solved within a couple of minutes in Simulink, but cannot crack for a couple of days in LabVIEW. It is a Rising integrator (model and plots from Simulink attached). Mod is the modulus function (i.e. remainder), the integrator reset is triggered by the external “Trigger” signal at 1 sec. After that, as you see the integrator generates a ramp signal.

I was trying to represent the same behavior in FPGA LabVIEW in order to use it further on my cRIO. I’ve seen on the forum, that one of the most feasible solutions for the Quotient & Remainder function (i.e., Modulus in Simulink) is the use of a while loop system with subtraction. But the behavior of the system is different since it generates a ramp signal after the reset is on, but it has a negative slope and saturates at -37k.

Just to check in general how the approach works in LabVIEW, I’ve designed the second model with a Quotient & Remainder block (I know that for FPGA it is not the best option, plus I could not figure but how to use it with FXP values). But this model generates the output with a value of 5. Which is even more questionable.

In this case, could you please advise what I am doing wrong with the FPGA code for the block? Since FPGA is the main reason, why I am looking for any options but not to use the Quotient & Remainder block. Thank you in advance.

P.S. The models are designed in LabVIEW 2014 SP1.

[SSPTest]

Hello Esturov,

I opened up your integrator LabVIEW functions VIs and just had a couple of questions to start. 

1) It looks like in the Integrator_while_loop.vi you're using a feedback node right after the Discrete Normalized Integrator block. I'm wondering why you put this here and what value you're hoping to pass (the value from this run or the last run). 

2) You indicated that one of these generates a ramp signal but has a negative slope and the other outputs a value of 5. Which VI corresponds to which behavior? 

3) I believe you were referring to this previously, but have you looked at this article?  It shows how to create similar behavior to the modulus you're describing in LabVIEW

4) Have you tried running this with highlight execution so you can see where the values are becoming inconsistent with the modulus function? A list of debugging tools in LabVIEW can be found here. 

Please let me know about these questions. 

Best

Zoe B.

[ESturov]

Hello SSPTest,

1. I did not put the node there on purpose. Since I have the Integrator output signal goes to the while loop and to the selector, the node appears itself when I am wiring the output. And I am looking to past the current value (from this run) as the output signal.

2.1st Paragraph - Integrator_while_loop and 2nd Par - Integrator_SGL.

3.  The article does present the modulus, by simply using the Quotient&Remainder block. For FPGA this block is usually not applicable due to the constant delay that it will cause during the operation. That's why I more focus on the issue described in the first paragraph. That's why the system with a while loop was implemented and tested as the main one.

4. Yes I did use it. And now I realise that the problem with the integrator and the trigger reset signal. Looks like the behaviour of the integrator is different from the one in Simulink. I deleted the wire that passes a signal to the integrator reset, and now I have a behaviour of the system that I was looking for.

Thank you for your tips!