Rio underflow error

[tomnz]

I get error 5001  CRIO Module Underflow. This error occurs if post-processing code on the FPGA VI cannot execute in one acquistion period.

What exactly is post processing? Does this just mean the overall execution time on the target is too slow because it has too much to do?

I tried reducing the sample rate to no avail.

Thanks

[Jeff-P · Accepted solution]

Hi tomnz,

Underflow normally means that you are not putting enough data into the FIFO and on the host side the FIFO read is timing out. Try doing some loop timing in your FPGA data acquisition loops to see how fast you are acquiring data and loading it into the FIFO. Also on the host side, monitor the timeout on your FIFO read to see if it is timing out.

Hope that helps!