Rio size

[tomnz]

I am using a Crio 9114 chassis and a cRio 9022 which I realise isn't exactly the latest version. I am trying to do some adaptive signal processing and very quickly have hit a size barrier. of course I can reduce the size of my arrays and fiddle things here and there but I appear to be a long way off.

I attach the error compilation thing after 6 hours!

Do you have a device which can handle this size of problem (which I consider not too big really). I probably need one 12 times bigger than present

for future work. Still, I like the technology and it has a great future.

regards

Tom

[GregFreeman]

Arrays on FPGA is generally not suggested. You need to post your code if you want people to let you know how to optimize. 6 hours is a long time; you need to change your architecture.

[tomnz]

Well you may well say that and I appreciate your quick response, but I am learning from LabViews own examples. Here is a VI from LabView's library which simulates a linear discrete system. The order appears to be limited to 9 for this example.  Now simplify this and imagine an FIR system only but of order say 1000 taps. How do you get rid of the arrays without doing it element by element and having a program teh size of the Eiffel tower? Apologise for the typo in the question, it was only 2 hours and not 6 to compile.

Thanks

Tom

[Doug-B]

Hey tomnz,

Looking at your code, there appears to be quite a lot of data manipulation that you are doing on the FPGA. I would suggest trying to move much of that data manipulation off the FPGA VI and onto the Real Time VI by using shared variables and FIFOs. Also, if you could let me know what example code you started with that would be great to know so that I can take a look at that as well.

Thanks,

Doug B