Dear,
For the project I uesd a compact rio 9002 with the NI9411 slot.
My question is about the seize of the ressource:
Is it a RAM seize problem or a the FPGA hard drive problem?
Thank you in advance
Compilation failure:
Status: Compilation failed due to resource overmapping.
The FPGA VI does not fit on the FPGA target because the VI requires more resources
than are available.
Suggestions for eliminating the problem:
* Reduce the amount of logic in the VI
* Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram
* Change arbitration settings
* Use Timed Loops instead of other loops
* Use Timed Loops for resource-intensive sections of the block diagram that
do not require any looping
* Recompile
Number of Block RAMs: 64 out of 40 160%
Message Labview FPGA compile:
This mapped NCD file can be used to evaluate how the design's logic has been
mapped into FPGA logic resources. It can also be used to analyze
preliminary, logic-level (pre-route) timing with one of the Xilinx static
timing analysis tools (TRCE or Timing Analyzer).
Design Summary:
Number of errors: 1
Number of warnings: 73
Logic Utilization:
Number of Slice Flip Flops: 1,782 out of 10,240 17%
Number of 4 input LUTs: 2,902 out of 10,240 28%
Logic Distribution:
Number of occupied Slices: 1,893 out of 5,120 36%
Number of Slices containing only related logic: 1,893 out of 1,893 100%
Number of Slices containing unrelated logic: 0 out of 1,893 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: 3,106 out of 10,240 30%
Number used as logic: 2,902
Number used as a route-thru: 204
Number of bonded IOBs: 149 out of 324 45%
IOB Flip Flops: 13
Number of Block RAMs: 64 out of 40 160% (OVERMAPPED)
Number of MULT18X18s: 2 out of 40 5%
Number of GCLKs: 2 out of 16 12%
Total equivalent gate count for design: 4,238,602
Additional JTAG gate count for IOBs: 7,152
Peak Memory Usage: 175 MB
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
