Read memory inside a timed loop

[User_OP]

I’m sending data from host to target using a FIFO, and then I stock them in a memory, which I will need to read from each time I need my data, the problem is that it must to be inside a timed loop, but when I tried to read in that case I got an error as shown in the screenshot. I don’t understand the problem exactly nor how to fix it !!

[GerdW · Accepted solution]

Hi User_OP,

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@User_OP wrote:

when I tried to read in that case I got an error as shown in the screenshot. I don’t understand the problem exactly nor how to fix it !!

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Did you read (and try) the solution given in the error dialog "Details"?

Have you tried to wire the output of the ReadMemory operation to a shift registers instead of an indicator?

Btw. when you would use AutoCleanup then your VI would require just 1/3 of the screen instead of more than one FullHD screen…

[JensG69 · Accepted solution]

You defined yourself, that you need 2 cycles before the data of a memory item becomes available:

Use a shift register as Gerd suggested (but then with 2 cyles) or decrease the number of read cycles to 1.

For further details I suggest to have a look at the example

"Memory with Cycles of Read Latency.lvproj" from the NI Example Finder

Regards, Jens

Regards, Jens