RTL elaboration failed flexrio PXIe-5763

[itst1357]

Hi,

I am getting an error while trying to compile LabVIEW code for installation on an FPGA board. 

The error is: 

RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
16 Infos, 24 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
::RTL Elaboration failed
while executing
"source -notrace ./.Xil/Vivado-30684-ip-10-0-59-151/realtime/MacallanTop.tcl"
invoked from within
"synth_design -keep_equivalent_registers -top "MacallanTop" -part "xcku040-ffva1156-2-e" -flatten_hierarchy "full""
(file "/opt/apps/NIFPGA/jobs2/DSZOpaT_XX5t9Db/synthesize.tcl" line 32)
invoked from within
"source "/opt/apps/NIFPGA/jobs2/DSZOpaT_XX5t9Db/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Thu Aug 26 06:43:56 2021...

It seems to go away if I don't transfer a 2048-entry array into another clock cycle loop using a FIFO. However, I need this 2048 array to do signal averaging to a time-dependent (2048 entry long) signal, and I need to send it to another loop because I cannot transfer the 2048-long array over a DMA target-to-host FIFO as 2048-long arrays are not an option. The best I can do is move the array to while loop from the SCTL, split it into chunks of 16, and transfer them one at a time. And I cannot do this in the SCTL because you can't put a FIFO inside a for loop inside a SCTL in LabVIEW FPGA.

Please help! I've been trying different strategies for days and still haven't figured it out.

[Terry_ALE]

Stepping back, what are you looking to do?

[itst1357]

Hi,

Thanks for the response. I am trying to capture a signal that is repeating in time (approx every 10 microseconds) in 2 channels (in-phase and quadrature) at 250 MS/s. Onboard the FPGA I want to phase correct each incoming time window (10 us) and then coherently average each 10 us window during 100 loops. I have gotten the phase correction working with the data in chunks of 32 entries for each channel, but the signal averaging needs to be in sets of 2048 (the whole time sweep). So I need to store a long array and add to it in shift registers as well as keep track of the number of times I've added to it (I think, unless there is a better way to do this averaging). This all works pretty easily. Problem is, once I've done 100 loops, I want to send this "averaged" (summed) array to the host computer and I can't figure out the proper way to implement this without error.

Thanks,

Brad

[Terry_ALE]

Have you tried storing the data in memory based on block RAM (BRAM)?  That should be able to hold that amount of data.

[itst1357]

Hi, do you mean block memory? I only see DRAM, LUT, and Block Memory as memory item options. When trying block memory I get this error about 5 mins into compilation:

 Details:
ERROR: [IP_Flow 19-3458] Validation failed for parameter 'Write Width A(Write_Width_A)' for IP 'ReallyLongUniqueName_ReallyLongUniqueName'. Value '65536' is out of the range (1,4608)
ERROR: [IP_Flow 19-3461] Value '65536' is out of the range for parameter 'Write Width B(Write_Width_B)' for IP 'ReallyLongUniqueName_ReallyLongUniqueName' . Valid values are - 2048, 4096, 8192, 16384, 32768
ERROR: [IP_Flow 19-3461] Value '65536' is out of the range for parameter 'Read Width B(Read_Width_B)' for IP 'ReallyLongUniqueName_ReallyLongUniqueName' . Valid values are - 1, 2, 4, 8, 16, 32, 64, 128
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'Disable Collision Warnings(Disable_Collision_Warnings)' with value 'false' for IP 'ReallyLongUniqueName_ReallyLongUniqueName'. User configuration exceeds BRAM count in the selected device
INFO: [IP_Flow 19-3438] Customization errors found on 'ReallyLongUniqueName_ReallyLongUniqueName'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

I tried using DRAM, LUT, and registers as well and they all give their own errors too. Do you know if there is a 'correct' way to transfer 2048-long 32 bit fxp arrays between clock cycles that I should be troubleshooting to make it work? Is this block memory?

Thanks for your help,

Brad

[Terry_ALE]

You may be at the limits of the Block memory.  In this case you can use DRAM for storage but pull the data into the chip via block memory to keep latency down.