RT Synchronizing a Timed Loop to External Trigger

[Antipholus]

Using LV 8.5.1 with cRIO FPGA and RT.

I am using an 1PPS external trigger that is read by a cRIO digital module and passed to the RT code. The 1PPS pulse width is only 65us, so I am using handshaking between the RT and FPGA to insure the read every time. That works very well. I need that trigger (in the RT code) to initiate a 640 ms process that MUST start within 3 ms of the leading edge of the trigger.  In a regular while loop, the loop timing varies +/- 10 ms... so that won't do.

I can make the process occur VERY precisely (of course) with a timed loop... but only asynch with regard to the 1PPS. So, what I need is an idea how to synch the timed-loop using this external 1PPS... or without a timed loop, some other way on the RT of a cRIO to get the timing consistency to +/- 3 ms.

[Jarrod_S.]

What have you tried in terms of interfacing the digital trigger with a regular while loop? One option would be to have a regular while loop that implements your 640ms process that waits indefinitely on an IRQ that your FPGA code fires when it detects the trigger event. You should get good timing much less than 3ms with this approach, unless there is higher priority code running.

There is no way to set up a timed loop to trigger based on an FPGA event such as an IRQ. LabVIEW 8.6 introduced new functionality to allow software-triggered timed loops. In this case you could have your main loop poll the digital trigger result from the FPGA and if it's True, then you fire the trigger for the software-triggered timed loop running in parallel. This would also give you good timing results, although the latency would now be based on software execution instead of hardware.The latency itself should be deterministic if your code is written correctly, but the overall latency might be higher than a hardware-based solution.

Message Edited by Jarrod S. on 11-14-2008 12:25 PM