Hi to all,
I’m working on two large applications that both use FPGA (PXI-7831R). The first one has three FPGA, each with a different load, and contains 1052 user VIs. The second application has one FPGA and contains 770 user VIs. In both applications, when I recompile an FPGA and I refresh the FPGA reference, all VIs are still ok. Note that at this time the top level VI is opened and that I do “save all” and “close all” after the refresh.
But now, if I edit any VI using one of these FPGA references, I’ll get an FPGA Read/Write Control with no control available, all my control disappeared and my wires are bad. Also, I can’t build an application from that top level VI. The only way I have found to correct that problem is to do a “ctrl-shift-run” on the top level VI after the refresh and then, save all. Is that normal? Does any one else has this problem?
I’m using NI-RIO 1.3, VISA 3.3 and LabVIEW RT 7.1.1.
Thanks!
Patrick.
