Problem in configuring and initializing FPGA

[ali462]

Hey, I have a Problem in initializing my FPGA, any suggestions?

Attached the real time and intializing VI

[GerdW]

Hi ali,

which problem to you have?

Unfortunately you didn't attach the project file so we cannot examine the type of FPGA you are using. But I guess a FIFO size of 1M is rather large…

[ali462]

Hey,

Attached the Project file. Thanks

[ali462]

The Problem is I can Interface the Real-Time with the Host PC inorder to Display the evaluated data

[GerdW]

Hi ali,

The Problem is I can Interface the Real-Time with the Host PC inorder to Display the evaluated data

What is the problem when you can interface the RT target?

[ali462]

Hi,

I'm sorry, it was a typo. I can not interface**

No values displayed(image attached)

[ali462]

Hi,

Image attached for the FPGA-SENT Logger with CGS Modul V02.

It is displaying the data but not on host Pc

[GerdW]

Hi ali,

It is displaying the data but not on host Pc

How is that "pc" related to the RT and FPGA target?

(I didn't knew about the "Mobility" branch of 1stSensor. Glad to learn about them.)

[ali462]

Hi Gerd,

Thank you for your Kind words.

I have attached the Project above, you can see it in the Host_Main Vi. Can you suggest something so that so that I can see the evaluated data in the Host_Main aswell? It's being displayed correctly in the FPGA.main.  Any help would be greatly appreciated. Thanks

[GerdW]

Hi ali,

I have attached the Project above, you can see it in the Host_Main Vi.

The VI is no project file. Such files use a suffix of ".lvproj"…

Can you suggest something so that so that I can see the evaluated data in the Host_Main aswell? It's being displayed correctly in the FPGA.main.

LabVIEW comes with a huge library of example VIs and projects.

And there are examples showing how to transfer data between host PC <-> RT target <-> FPGA!