12-12-2012 04:16 PM
Hello, I'm using LV 2012 with a PCIe-7852R board and would like to do something simple sounding but likely complicated. I would like to output two 80MHz square waves with a programmable phase delay between them that goes from 0 to 2 ns in 100 pico seconds step, or there abouts. Using SCTL this is no problem but the step size is restricted to the nanosecond regime using FPGA derived clocks. This board has a Vertex-5 chip which appears to have DCM that allows clock phase shifting. Is there a simple way to do this without learning VHDL or getting far into the details, or should I plan on a long road?
Thanks,
Ed
12-13-2012 02:36 AM - edited 12-13-2012 02:37 AM
This won't be possible.
100 picoseconds resolution requires a frequency of 10GHz which certainly won't be achievable. We have code running at 200MHz (5ns) and this is pretty close to the limit. I think the board you're referring to might support 400MHz (or maybe 500MHz) but I doubt it'll go beyond that at all.
You can see what the maximum frequency of a clock is you can generate and use that to create your outputs. The resolution of the phase shift will be limited to the fastest clock you can define.
You also don't say what you want with "output" Do you mean DIO or just defining two different FPGA Clocks? They are not the same thing.
Back int he old Analog world, you can create such delays through engineering different cable lengths... Simple signal propagation delay will give you better control of the delay but it's obviously not choosable programatically.
Shane