PXIe-7962R on-board RAM timing

[xristos86]

Hello everyone,

I am working with PXIe-7962R on a project for which I have written custom VHDL code and inserted it into the design using HDL Node.

I need to access the on-board (512MB) RAM and I am doing this by connecting my custom unit with the memory pins within LabVIEW.

However, I need to at least know some basic information about the timing of the RAM, because the timing is tight and I can't just poll the read strobe pin. I need to know beforehand how long the first read and each subsequent read takes so that I can schedule the operations I need to perform.

Does anyone have the information I request or is there a datasheet with the timing diagram of the on-board RAM?

Thank you for your help!

[Hossein128]

Hi,

I have some question about your request.

Could you provide me with further information? What version of LabVIEW FPGA are you using?

The memory timing is deternined by the clock under wich the DRAM memory I/O node runs. It will run very quickly in my experience (I've seen reads and writes occur at 125MHz), but his speed needs to be determined by the requirements of his code.

How quickly does your HDL code have to read or write memory? How quickly are you running your HDL node? I believe the HDL node timing is slightly different from the timing in the overall FPGA VI. You'll need to check the detailed help for the HDL node to find more information on that.

Hope that helps!

Best regards,

Hossein

[xristos86]

Thanks for your reply!

First of all, I'm using LabVIEW 2009 SP1.

Second, I'm not really using memory read/write methods to access the memory, but I'm accessing the pins "directly", just as you do with the DAQ module inputs/outputs by dragging and dropping them on the schematic.

Finally, at this point the attainable speed of my module is a little higher than 100 MHz, but there is no real limit to the speed I want to read/write as other parameters of the experimental process are determined by that. What I am actually asking for is not the speed of operation or the bandwidth of the on-board RAM but its timing cycle-by-cycle so that I know exactly when my data is available without using the read strobe signal as the latency of the memory directly affects the rest of my design and I need it to be specific and not variable or unknown.

I hope I 've made myself clear.

[Hossein128]

Hello,

Are you developing a custom adapter module? Can you provide me a list of your hardware and software? We'll likely need to get the PSE involved if you are doing custom module development.

Based on your description (accessing the pins "directly", just as you do with the DAQ module inputs/outputs by dragging and dropping them on the schematic), it sounds like are using I/O nodes from the CLIP. If you are interacting with the memory through the FPGA diagram, the latency will be controlled there. If you are accessing it directly through VHDL in your CLIP, then I honestly don't know.

Can you give me complete hardware/software configuration in regard to the FlexRIO and adapter module?

Could you also provide a screen shot of the code you are using to access the DRAM? Is it directly from your CLIP/VHDL, or on the block diagram of the FPGA VI?

Regards,

[Hossein128]

Hi,

Did you solved your problem?If not, could you give me the info that I mentioned in my last reply?

Thanks and hope hear from you.

Regards,