[PXIe-5785] Acquiring at 6.4 GSps... how?

[DoesntMeanAnything]

Hello there.

Regarding the example design ("Getting started"), I am trying to acquire samples at a rate of 6.4 GSps instead of 3.2 GSps without success.

There is not much documentation accompanying the board and this AR is pretty useless.... From that however, I understand that I have to modify the "ADC Interleaving Factor" value from 1 to 2 in the "FlexRIO Properties" node. In addition, the linked AR refers to other changes to be implemented in the LVFPGA design. Having a look at the top VI of the "Getting Started" library (LV 2019), I can only find a "flexrio.io.interleaving factor 0" (is it the same? not quite sure...). This value only is passed to the VI "Analog Trigger with Interleaving Select" and "AI Select Channel" VIs (but it is NOT used inside the latter).

I read the data-sheet of the ADC12DJ3200 mounted on the 5785 board and it seems that in single-channel mode, the input is indifferent (but recommended IN_A channel... I guess it corresponds to AI0) and are phase-shifted by the ADC itself. It's not clear to me but I think at this point that the data is still passed to LVFPGA as separate AI0 and AI1, but whose alternate data refer to a single channel and therefore to be interleaved at output stream. Is it correct?

[DoesntMeanAnything]

Trying to formulate again and explain better my problem.

I've set the interleaving factor from 1 to 2 and passed it to the ADC but I'm not receiving half of the samples (ofc, the FPGA design shall be updated to suport it).

Here is the acquisition chain:

Acquisition chain

I have circled the channel data generation on the left and underlined the DSP processing chain on the right.

Here is the channel data generation VI:

TLDR; The problem is: if I interleave the channels data, my array fixed size grows from 16 to 32 and the following DPS chain only supports 16 sample per cycle (16 SPC)