P2P

[bahec666]

Hello. I have a system that contains: chasis pxie-1082 with ni pxie-7966R fpga and ni pxie-5451 generator.

I want to transfer data from host to pxie-7966R, using DMA FIFO Host To Target, and to transfer data from pxie-7966R to ni pxie-5451, using peer-to peer streaming. I am created fpga vi, which receieve data from host with dma fifo in one single-cycled timed loop and transmit data to pxie-5451 with p2p fifo in another loop.

So, i'm running application and see on oscilloscope, that sometimes signal dissapears. I think, that pxi lines havn't enough speed or fpga not support host to target and p2p simultaneously.

 Can you tell me, does pxie-7966R supports host to target dma fifo data transfer simultaneously with peer to peer data streaming to generator pxie-5451. And how i can increase performance of this system?

It is a host vi on the picture.

[Bob_Schor]

Please don't post screen shot images of part of your Block Diagram -- it doesn't help us much to find the problem, since (a) we cannot see the entire VI, usually (true in your case), (b) we can't examine all the cases of Case structures, (c) we can't see possible "bad wiring" you might have inadvertently hidden (I've connected wires that should have gone to an output terminal to an input terminal, and then wondered why my "output" was wrong), (d) we can't execute, and observe, your code in action, and (e) we can't easily modify your code to test fixes.

You are asking for our help.  Help us to help you by attaching the VI itself (among other advantages, we can see what version of LabVIEW you are running, allowing us to post suggestion code that you can open with your LabVIEW version).

Bob Schor

[David-A]

The 7966 has a maxmimum throughput of 800MB/s. So if you are sending data to the 7966 from the host, and you are sending from the 7966 to the 5451, then you have some combined data throughput you need to hit. What is that combined data throughput amount?

Even if it averages out to 800MB/s, if you briefly exceed that amount then you can overflow the buffers and drop samples. Also if you are approaching the maximum throughput of the device (>80% of max) then you are susceptible to data collisions in the backplane of the chassis then can momentarily lower you throughput and cause overflows. Streaming your data through DRAM can help smooth out both of those issues but it won't increase the maxmimum amount of data you can transfer to and from the FPGA module. 

[bahec666]

I'm sending 100 MB/s from host to FPGA and 400 MB/s from FPGA to generator. So, it doesn't exceed maximum data rate.

But now, when i'm sending one 16-bit data integer from FPGA to first channel of generator with data rate property - 100 MHz, there is an error, that P2P buffer is underflow. When i'm decrease data rate from 100 MHz to 50 MHz everything it's ok, but it's not desired frequency. I need 10 ns between two samples.

[Bob_Schor]

You are sending points one at a time?  Sounds like an "underflow" to me!  Generally one wants the hardware to handle data in "chunks" (chunk > 1), though your requirements might be different ...

Bob Schor

[bahec666]

I'm sending two points to one channel and two points to second channel.

I'm attachint my simple LabVIEW 2014 project. I'm reading uint8 numbers from big file (5-6 GB) and sending it to FPGA.

In FPGA i'm doing some processing and sending result to DAC. To simplify my project i removed processing, but it doesn't work.