Output frequency

[Amay01]

Hello everyone,

i am a beginner in working with a CompactRIO system and LabVIEW.

I am working with the cRIO-9035 and the analog output module NI 9264.

In my main project I had some problems to get the filters work correctly. So I tried to get a little test project running, but actual failed.

I am trying to generate a rectangular signal in my host.vi, transfer it to my fpga.vi via a FIFO and then give it out through the analog output module. In the host.vi every thing is working fine. But when I measure the signal which comes out of the module with an oscilloscope, the frequency is completly wrong.

I tried to put the output in a loop and control the time with a loop timer (red box). But this actually didn´t work.

Is there anybody who can say me what I am doing wrong or has some tips for me, what I could try?

Thanks and regards Amay

[crossrulz · Accepted solution]

It would be a lot more beneficial if you attached your entire project (project file and VIs).  There are way too many details hidden here.

But my first red flag is you are not telling the Square Waveform.vi what the sample frequency is.  That needs to match whatever you are trying to output.

The second red flag is all of the coercion dots on the transfer path.  A waveform changing into a U32?  Hopefully that converts correctly.  A U32? to a Fixed Point of who knows what scale is also worrisome.

[Amay01]

Thanks crossrulz for your answer!

It seems the missing sample frequency was the problem for the wrong output frequency in this little project.

I thought I was working with the standard values of 1000 as default if I dont give any other information. But apperently this was not the case.

Thanks for the hints regarding the datachanges. I tried to fix that. But I don't now how it is the clean way to write the waveform values into the FIFO. Because I need the values in the FIFO as FXP to be able to give the them out? If I try to use other data types I am not able to transfer the values.

regards amay

[crossrulz]

Start by setting your FIFO data type to match the FXP type as the analog output node.  This would eliminate the coercion in the FPGA and I would have more confidence in the auto coercion on the host side then.