Observe and collect sine waves

[cbutcher]

Here's an example of what I meant regarding the FXP coercion. I don't know that this is necessarily true, but I think it could be the source of your problem (maybe).

The "Number to Boolean Array" produces 16-element boolean arrays for each value, then the Boolean Array to Number expects 48 bits to be the input in order to interpret it as +-,48,24. As a result, I think the extra values as set to zero and the scaling becomes very small.

I added a small value to each of the 2nd and 3rd plots to make the output a bit clearer.

[cbutcher]

Hmm. I tried creating a simulated FPGA setup with your code and didn't observe the same problem. So now I'd ask another question - are you sure the wires are correctly connected to the AI0 input?

Sorry to ask a silly question but perhaps worth checking.

Here's the backsaved copy (to 2016, because that appeared to be the version you're using) of my modified project with an added "FPGA_Simulation.vi".

[CIel123]

Thank you very much for your help!

Let me understand your reply. I will try and learn from your project.

In fact, I'm sure my signal is connected to AI0 well. Because I tested it with other items in other forum posts (I can see the incoming sine wave), but when I wrote it myself, my VI was still an old problem (AI0 display port and waveform is a constant value). 

I put the two projects into the compression package. Could you please see what is wrong with my VI.

Best Wishes!

[cbutcher · Accepted solution]

Hi again,

I tried to open the project you attached but was unable to get any part of the project or VIs in the "Invisible waveform" folder to open. I initially thought this might be related to the project name and a lack of language support on my system, but I'm not so sure - the Data.lvproj opens fine and also contains non-ASCII characters for several items (e.g. names of things like the targets and the IP Builder section) and that loads fine (although there are some "?" characters in my display).

Are you saying that when you use the Data.lvproj + Host.vi + FPGA.vi, your code and system works as expected, but that when you use the other project it produces only a constant high voltage (~10.5V, which I think is probably the upper limit on the input), and you haven't changed any of the wiring/hardware setup?

If so, I think you might need to try opening a service request - I can't see what's wrong but I guess something is maybe corrupted/broken somewhere... 😞

[CIel123]

Hi,

I tried to write my LVPROj corresponding to data.lvproj. You saw that  ''?'' It could be Chinese characters (sorry).

I think it's basically the same everywhere as data.lvproj, but output 10.5 (AI0 on FPGA VI). As for NI services, I've basically turned them on.

I'll try to send the invisible waveform.lvproj again. I hope to get your help. Thank you!

[cbutcher]

Hi again,

Sorry - I still can't open it. I tried replacing any remaining characters with their English equivalents using the working "Data.lvproj" as a guide, but that didn't help.

Then I tried moving the working "Data.lvproj" from your previous upload into the directory with the "Host.vi" and "FPGA.vi" (neither of which will open for me outside of the project either) and then the "Data.lvproj" file also failed to open (probably because it linked to the "invisible waveform" project's Host.vi and FPGA.vi.

So it seems that those two VIs are broken for me and I can't open them. I don't know what might cause this. I get the following prompt when trying to add Host.vi or FPGA.vi to a new blank project (this is for FPGA.vi):

I don't think the language necessarily the problem - I think that usually VIs should open fine and just the strings in labels and captions can be broken if the opening system (i.e. mine) doesn't have the necessary character support installed (via LabVIEW language choice - not OS support).

Were you able to open a service request?