Need to compile FPGA code after SVN checkout , why ?

[sv123]

Hi,

Our project uses a FPGA. Lets say, we compile the FPGA code on computer A. The code is working fine, so we upload the code to a SVN server where the whole project folder (including the FPGA Bitfiles folder) is stored in the repository. Now lets say we delete the project folder from computer A. Then, we checkout the project folder from SVN onto computer A. Now if we open the project, VIs that use FPGA code have broken links. The error says that FPGA code is not compiled. I dont seem to understand what is going on and why a perfectly working code stopped working. The same problem also occurs if we checkout the project folder onto say computer B.

What I have noticed is that after we checkout from SVN, the dates and times on all the files is changed to the current date and time. Is there something that depends on date and time of the files when it comes to FPGA compilations ? It is very frustrating, because the compilation takes more than 4 hours.

Any help will be greatly appreciated.

Thanks,

Best,

Saumil

[MarcoMauri]

Are you storing the compiled code in the VIs of your project?

Maybe it's something related to that...

[sv123]

Hi,

The compiled code is stored in a seperate file in a FPGA Bitfiles folder. The folder is part of the 'Acquisition' folder and is thus a part of the SVN repository. I think the reference to the compiled code by VIs that use that code must be using an identifying mechanism that is tied to the physical location of this file and not just the name. And I have no idea how to fix this, it just seems wasteful to recompile the FPGA code everytime the project folder is installed on a different computer or even if the folder is reloaded onto the same computer.

Saumil

[MarcoMauri]

I wasn't clear in my question, sorry.

I'm asking if you use the option "Separate Compiled Code" in your project:

http://zone.ni.com/reference/en-XX/help/371361H-01/lvconcepts/saving_vis_compiled_code/

Regards,

Marco

[sv123]

Hi,

I just checked, the FPGA VI was unmarked, so it did contain code. I have marked all the VIs to seperate the code from the VI. I am trying to see if this works. Your directions were very helpful, this is exactly what I was looking for.

Thanks, and I will get back as soon as I know that this was the problem.

Best,

Saumil