Need to build FPGA bitfile twice

[cbutcher]

When I build my cRIO/FPGA project's FPGA build specification into a bitfile, the output immediately complains that the bitfile doesn't match (and the project has the dirty star mark).

If I try to close the project, I'm told that an item was added, an item was moved, and an item was removed.

Building a second time (without making changes) results in a happy project. Alternatively, (iirc) I can change the Open FPGA VI Reference to reference the specific bitfile, and all is well (it's currently referencing the Build Specification).

The RT subVIs make use of the bitfile via a typedef to the reference, which also targets the Build Specification.

Opening two of the FPGA VIs' windows then closing them immediately result in the project having changes (the same Added, Moved, Removed combination). These are the top-level VI, and the VI (called by the top-level VI) that does most of the work (SPI communication).

Is there something obvious I'm messing up here? The bitfile appears in the RT Dependencies, but nowhere else that I can see.

[kartiknattar]

Kindly upload your FPGA project.

[cbutcher]

Should checking the signature cause a project change? Seems a bit odd.

Still open to hearing other ideas on this problem - working on tidying project for sharing but if possible would prefer to avoid uploading - producing a minimal working example is a bit of a pain because it's not clear what's causing the problem, and removing things might lead to accidentally fixing the issue.