NI Sync Create Clock Issue

[bchang32]

I am trying to use NI-Sync to create a clock to then send triggers to an output. From looking at the example Here , it should work. However, I am getting the error of 

"Property Node (arg 1) in niSync Create Clock (Frequency).vi:6780001->triggerMultiplySandbox.vi <ERR>
This operation requires a feature that is not supported."

So it looks like its erroring at the create Clock.vi. I believe I am following all the rules, so it should work? See attached for my vi.I've set the frequency from 10 KHz to 1 MHz to see if its maybe a frequency issue. The coerced freq is always inf 

[Alexander_Sobolev]

A few guesses:

Should not it be /Dev1/PXI_Trig0? 

What is 430S-007-EndPXI? 

What board is Dev1?

Just in case >> Make sure that the board is in the timing slot of the PXI chassis (slot 2).

[bchang32]

So it should be /Dev1/PXI_Trig0 (I realized after I posted it), but it still didn't work.

Dev1 is the 6674T timing card and it is inserted in the timing slot. Why should it be in slot 2? Should it be in slot 4, the timing slot?

I'm using the PXIe-1082

[TylerK · Accepted solution]

Hi,

The onboard clock gen of the PXIe-6674T is a DDS and which does not support niSync Create Clock.vi to generate clocks. To generate a clock with the PXIe-6674T, use the DDS Properties>>DDS Frequency property node then route the DDS to the designed terminal. You can route the DDS directly to some terminals like ClkOut, PXI_LVDS#, and PXIe-DStarA#. For other terminals, you'll need to set the synchronization clock to the DDS and then route the synchronization clock as the source.

For example to generate a specific frequency on PXI_Trig0 with the PXIe-6674T, you would take the following steps:

1. Set property DDS Properties>>DDS Frequency to the frequency
2. Set property Synchronization Clock Properties>>Synchronization Clock Source (PXI_Trig, PXI_Star, PXIe_DStarB) to DDS
3. Route Synchronization Clock (Full Speed)/SyncClkFullSpeed to PXI_Trig0

In the PXIe-6674T User Manual, you can find a summary of all the possible routes in Figure 7. Sources and Destinations for PXIe-6674T Signal Routing Operations.

Also, I'd recommend leaving the PXIe-6674T in the system timing slot of your chassis which is slot 4 for the PXIe-1082. For PXI-1 chassis, the system timing slot was often slot 2, but for PXI Express chassis the system timing slot can vary based on chassis model.

I hope this helps,
-Tyler

[bchang32]

Thanks! 

Is there a way for the backplane clock to generate a 200 MHz clock then? I want it all to be synchronized to the backplane. Is there a way to multiply or oversample the clock?

I tried doing what you said but initially it didn't work. Turns out, I had to make sure I had the right synchronization sources. In this case since I was outputting to a PFI, I wanted the synch source to be the front.

[bchang32]

Also I noticed that the output is a sinusoid at 200MHz but not at <50M. Is there any way to make it all square?

[sravicha]

Could you explain in more detail what you are trying to do with your application?

What do you need to be synchronized to the backplane clock and is the backplane clock disciplined to an external source?

Also, different terminals on the 6674T support different ranges of frequencies. The spec for the device is a good starting point. PFI terminals support upto 150 MHz. Performance above this frequency is not guaranteed. That must be why you are seeing the sinusoidal wave.

[bchang32]

I want to generate a 200 MHz clock to route throughout, but we want it to be a digital signal/square waves. I tried it at 150 MHz and it appears sinusoidal as well. 50MHz seems the closest to a square and its still pretty noisey.

We ideally want everything synchronized, so we have a 10 MHz clock connected to the 'ref in' in the back of the chassis.

[sravicha]

Have you considered routing the generated signal from DDS to the PXIe_DStarA terminals, which support high frequency clock distribution from the timing slot to each PXI Express peripheral slot in the chassis?

If you do need a front panel terminal output, how about the PFI_LVDS terminals, which are also meant for high frequencies?

[bchang32]

I have the 200 MHz outputting from the PFI_LVDS line to an oscilloscope (as a confirmation/comparison) and its still a sinusoid. I believe that even though it is a sinusoid, it is still triggering via the DSTARA line but I worry that there may be some mistmatch/skew, etc.