Multicore Programming with Simulation Interface Toolkit

[AnshB]

Hi ,

       I have issues running Multiple Model Dlls on separate cores on a 8108 Embedded controller.These models are the simulink models running at 300 us time steps (sampling time). I followed the help files for the SIT "Executing Multiple Model Dlls Simultaneously on Same RT Controller"and did exactly whats depicted in the help file.It works fine running 1st model in one core .The  problem arises when I am trying to run the 2nd Model on 2nd core of the RT ,I get the error-209802. This it seems is the error that is coming from the IO read vi ( created by SIT Connection Manger).I then remove the DAQmx Wait for Multiple sample.vi . After that I am able to run both the models in 2 Cores Simultaneously. But when I analyse the waveform in the oscilloscope I see that the models runs in default 20us sample time irrespective of whatever sample time u provide for the Model dll.Moreover the samples are distorted heavily.The default sample period (sample clock) I am using is 1000 us .

As per the error-209802 it says to slow down the sample clock . I tried slowing the sample clock from 1000us to 10000 us . Still doing that I didnt get the 2nd model running on the second core properly and ends up in a error-209802. The only circumstance it works is when I change the sample clock to 1000 us and the model sample rate to 2000 us (2 ms).But then this is not what I want . I need to run both the models on both the cores simultaneously at 300 us. Let me know if I can do this on the RT and if yes whats the method I should follow .

Summary :

Need to run 2 model dlls on 2 RT cores simultaneously on a RT controller.

NI PXI Chassis : 1042

RT Controller used :PXI 8108

Analog Output Card : PXI 6713

Sample Clock : 1000 us .

Generation Mode : Hardware timed single point (also used Finite and Continouse Sample mode)

Model Sample Time :200 us .

SIT Port used : 6011 (1st model) and 6017(second model)

Ciao

Ansh

[DiscoBall]

Hi Ansh,
 

We are looking into your issue, can you you give us more detail about the application, could it be a canidate
for NI VeriStand? Also, can you provide the following information:

1. Verions of LabVIEW, MATLAB, and what compiler (mex -setup) you are using
with Real Time Workshop
2. All files associated with the application
3. Can you detail what values you put into the controls on the driver VI and did you set them as default?

MATLAB® and Simulink® are registered trademarks of The MathWorks, Inc. Other product and company names listed are trademarks and trade names of their respective companies.

 

 

[AnshB]

Hi Joshua,

                 Thanks for your help.Following are the answers to your question

1. Verions of LabVIEW, MATLAB, and what compiler (mex -setup) you are using
with Real Time Workshop

MATLAB version 2007b, Labview version 2009 , compiler - MSVC compiler

2. All files associated with the application
 

The models which I was using are the same sine wave models in the SIT examples . You can take any sine wave generation model of simulink. In my case I was running two sine wave generation models having a step time of 300 us each but different phase angles.

3. Can you detail what values you put into the controls on the driver VI and did you set them as default?

I was only changing the step time of the model from default -1 to 300us.

I was seeing a typical case in this . Although the Basic loop rate (model step time was -1) it was not taking the model step time (300 us) so i have to mention it explicitly in the Basic loop Rate dialogue box. As far as the other fields are concerned I was leaving other fields as it is . Earlier I tried changing the loop timing attributes to different processors  (cpu 0 or 1) but then I dodnt see it happening in the LABVIEW RT console. So I  called both the drivers for the models i.e model1_driver.vi and model2_driver.vi in one master vi and ran both the Vis inside a timed loop structures and assigned different processors for different driver Vis.For this I had to change the sample clock period from 1000 us default to 500 us , so that I get to choose the 1 Mhz clock timing in the timed loop other wise if I keep the sample clock rate to default 1000 us I am not given choice for 1 Mhz clock in the timed loop structure I can only chose 1 kHz clock.I aslo made the driver Vis reentrant.

Let me know if the methods I followed are right or wrong . If wrong kindly let me know the correct methods to do so .

Thanks

Ansh

[DiscoBall]

Hi Ansh,

What version of the MSVC comipler are you using to build your models? Did you name your two models differently? Have you installed SMP suppport to PXI 8108? Can you attach your final project that contains both driver VIs and their respective host VIs?

Message Edited by DiscoBall on 05-07-2010 07:41 AM

[Stephen_S.]

Hi Ansh,

Did you have any of the information or files that Joshua was asking for? Let us know when you have more on this issue.

Regards,

Stephen S.