Memory error when compiling LabVIEW FPGA project

[Giuvan]

Hello!
I’m doing some tests with the timekeeper library which can be found in

https://forums.ni.com/t5/Sync-Labs/NI-TimeSync-FPGA-Timekeeper-Getting-Started/td-p/3543895

I’m using LabVIEW 14.0.1 32bit SP1 on a 64-bit Windows Server 2008, creating a project conceived for an MXI-e cRIO 9159. The compilation tools are Xilinx ISE 14.7

My topVI has:

1) The timekeeper.vi out of any structure
2) A SCTL that calls the Sync Time.vi for letting the HostPC synchronize the timekeeper
3) Another SCTL which simply calls Get Time.vi and Get Status.vi
4) An endless loop, timed with the Methronome.vi, which calls a subVI at a controllable rate; the subVI creates an array of 511 U64 elements and enqueues them, one by one, into a target-to-Host FIFO.

The intention is to timestamp the whole set, by placing the value returned by the Get Time.vi (read as local variable) as one of its elements.
When I try to build the project, after around 2 hours the compiler fails with the compilation error in attachment. It provides a suggestion on how to increase the memory from 2 to 3 GB, and reports that the current memory usage was 4Gb (i.e 0.5 GB); however the installed memory on this PC is 16GB and it’s fully available to the OS.
The code is very simple and it respects all optimization rules of the LabVIEW FPGA course, yet the compiler fails. What it’s puzzling is that it fails for lack of resources on the compiling machine, not because of insufficient resources of the target device.
Would you have any tips for me to avoid this from happening? Thanks!

[GerdW]

Hi Giuvan,

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@Giuvan wrote:

When I try to build the project, after around 2 hours the compiler fails with the compilation error in attachment. It provides a suggestion on how to increase the memory from 2 to 3 GB, and reports that the current memory usage was 4Gb (i.e 0.5 GB); however the installed memory on this PC is 16GB and it’s fully available to the OS.

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It doesn't matter if your OS can access the whole 16GB of RAM!

You are using a 32bit application, which is restricted to 2GB (or 3GB) memory usage. And it could fail even sooner as most often memory is fragmented into smaller blocks than required.

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@Giuvan wrote:

Would you have any tips for me to avoid this from happening? Thanks!

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Did you try the CompileFarm service by NI?

Can you attach your project so someone else might try to compile your FPGA sources to test the compiler?

Maybe we could even provide suggestions to simplify/improve the source code…