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MOSFET IV curve

Hi bhuyanashima,

 


@bhuyanashima wrote:

hello i am back with a new code for the same problem. 


You forgot message #7!

 


@bhuyanashima wrote:

we are intending to use RIGOL for DC biasing. we are getting the problem of OCP tripping. how do we solve it?


Set a larger current limit! (Or check for shortcuts…)

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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i didn't forget, i saved for previous version. It created C and D folders. 

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Hi bhuyanashima,

 


@bhuyanashima wrote:

i didn't forget, i saved for previous version. It created C and D folders. 


But the attached VI is still for LV2025...

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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