List of Labview 8 cRIO FPGA problems I'm having

[jeff_scharpf]

1) Empty Project does not find any hardware. If I open and empty project, then right click "New, Targets and Devices", the dialog box does not find my cRIO. If I create a RT project, the wizard finds it. The DMA demo instructs me to open and Empty project.

2) Adding I/O to the FPGA is not correct in the document "Labview FPGA Module Release and Upgrade Notes". It says to right click then select "New FPGA I/O". This does not work unless you first configure the FPGA by clicking "New C series modules.." then adding them to the project.

3) When working with an FPGA VI, the pallet can't seem to decide if it's an FPGA pallet or a regular Labview pallet. Numerous times I was trying to find FPGA functions and realized I was looking at a different pallet. Closing and opening the VI usually solves the problem.

4) RT VI keeps telling me that the FPGA VI is not compiled, even though it is, so I can't run the demo program.

I'm not sure if I'm doing something wrong. I'll probably be calling the NI support so I can get the sample DMA program running. 

Jeff

[jdigiova]

1) You are not right-clicking on the correct location in the Project Explorer window.  The demo you are following is assuming an FPGA device that is located in the development computer.  The Project Explorer window will mirror actual hardware since you are "finding hardware". Meaning that if the FPGA device is in the development computer you should right click on My Computer to add an FPGA device to the project because the FPGA device can actually be found in My Computer. However, for cRIO the FPGA device is physically located in an RT system.  So you must first create an RT system in the Project before you can add the FPGA device to this RT system.  If you notice the RT Project Wizard creates the FPGA device under the RT system, not My Computer.

2) Well the LabVIEW FPGA Module Release and Upgrade Notes are not incorrect either.  If you right click and select New FPGA I/O you actually do see some IO channels that are available by default for all cRIO systems (i.e  Sleep, Temperature).  However if you haven't added any C Series Modules to the project then you will not be able to create any IO for these modules.  So as you found you should add the C Series Modules to the Project before you try and add IO for these modules. The documentation you are referring to is for the software module and is trying to be as general as possible for all FPGA targets.  I recommend following the  "Getting Results with CompactRIO and LabVIEW".  You can find this document by going to Windows Start Menu>>Programs>>National Instruments>>CompactRIO>>Search the CompactRIO Bookshelf and searching for Getting Results. This document was designed with the CompactRIO user in mind specifically and will help you become familiar with the project environment.

3) In the bottom left of the VI panel you will see the target in which the VI is opened under.  With LabVIEW 8.0 you can have the same VI open under My Computer, an RT target and an FPGA target at the same time.  Now most of the time you wouldn't want the same VI open in all targets, but it is possible.  More often you can make use of this very powerful feature of LabVIEW 8.0 by having an FPGA VI and the RT Host VI open at the same time.  What this means is that the functions palette should change dynamically as you change between block diagrams for VIs open under different targets.  From you description it sounds as though the palette is not changing.  I assume either the VI is not actually targeted to an FPGA, or you have pinned the palette and are looking at a palette for the last VI you were editing rather than the FPGA VI.  If the VI is targeted to FPGA and you click on that VIs block diagram the palette should change.  If you can reproduce the behavior consistently and you are seeing palettes for windows or rt targets even though the VI is targeted to an FPGA then please contact technical support and help them try and also reproduce the issue with step by step instructions and configurations.

4) Now similar to question 3, there is a lot of work going on in the background to try and keep the FPGA VI and the RT host VI in sync.  Sometimes there are changes in the FPGA VI that do not get propagated to the host.  A compile should be propagated.  First you can be certain the the FPGA VI is actually compiled by right clicking on the VI under the FPGA device in the Project Explorer window and selecting Target-Specific Properties.  A properties window will appear and in the right pane you should see Bitfile information with either a path to a bitfile or "bitfile does not exist".  If there is not a path then the FPGA VI is not actually compiled and you need to recompile.  Please note some changes to the FPGA device in the Project after a compile will invalidate the compile.  For example, adding/removing IO to/from the project will invalidate the compile even if the IO is not used in the VI.  If a path does exist then you know that the VI is compiled.  Try and change which VI the Open FPGA VI Reference in the host VI is referencing and change it back to the original FPGA VI.  If you find a path to a bitfile does exist and you continue to get the broken arrow saying the VI needs to be compiled then please contact technical support with the steps and configuration. 

Regards,

Joseph D.

[jeff_scharpf]

Thanks for the replies Joe,

Yup, you were right on all points, lol. Everything is working great now that I point my targets to the right device. 🙂

I just finished some preliminary benchmarking compared to LV7 (cRIO throughput). I'm going to post these in another thread.

Jeff