Large Array Handling in FPGA

[D_A_N_A_S]

Hi,

I have two arrays of 300,000 elements, need to compare element wise and produce an output. If there is no difference (or less than a set value), count it as zero and then write how many consecutive zeros. If element is different (or greater than set value), write the same element.

Tried with LabVIEW functions and dll method. In Windows, when this VI alone is called, dll takes less than one millisecond and LabVIEW code (with LabVIEW Function method) takes 2-3 mS. But when it is called in a Real Time system (where so many parallel loops are running), dll takes 12mS and LabVIEW takes 25mS.

This RT system has FPGA; Sliced the array to 1000 elements and tried, but logic is not fitting in to this FPGA. How do I handle large arrays in FPGA?

Basically this array operation is for image comparison - Master Frame (Background Picture) Vs Captured Frame. I am able to compress 300kb to 5-20kb with this method, do you know any other logic to get a better compression in faster rate?

Any thoughts/suggestions?

Thanks

[Terry_ALE]

Which NI hardware are you using?  Large amounts of data are processed on an FPGA by streaming them.  That is, the entire array will not be on there at a given time.

There's a couple of shipping examples that demonstrate this on a FlexRIO.  See: \examples\FlexRIO\High Throughput\Streaming\High Throughput Streaming.lvproj

If you are using other hardware, this example can be ported to work on other targets.

[D_A_N_A_S]

Thank you Terry for the suggestion. I use CVS-1459.

Thanks

[D_A_N_A_S]

Hi,

When I have tried with cRIO-9101 (simulation mode); I got the expected result though it was taking time. But on the actual hardware (CVS-1459), same code gives different result. This piece of code takes longer time than the code without FPGA. Any recommendation to improve the timing? Any idea why does CVS give wrong output?

Thanks.

[Intaris]

For so much data, use the Host to Target DMA channel to hold the data. This FIFO exists on the FPGA (which I would limit to maybe 512 or 1024 elements, depends on your algorithm and hardware) but can be up to a Gigabyte or more on the Host (or RT) side.

The transfer from your host program to the FPGA (the interactions between the DMA buffer on FPGA and off the FPGA) is handled by the hardware driver.

If your software takes the elements when they exist and outputs them to another suitable DMA channel, you never actually need all the elements on the FPGA at the same time. OF course, if your algorithm cannot be implemented as a point-by-point algorithm, that approach may not work.