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Labview FPGA: Simulated execution on development computer is very slow.

I am working on an application that grabs frames from a camera using the Camera Link interface and does some processing on them using a FlexRIO system. Because it can take over an hour to compile the VI for the FPGA, I'd like to be able to test and debug changes to my code using the "Simulation" execution mode. My approach to this was to create a program that reads raw data straight from the camera, streams it via a DMA FIFO to the host, and have the host stream the data to a TDMS file on the disk. This part worked fine, and because the FPGA runs at 40MHz, I acquired nearly 1GB of data with several seconds of frame grabbing.

 

I then replaced the part of my main program that reads data from the camera with code that reads from a DMA FIFO, and added code on my host VI that reads from the TDMS file and streams it to the same FIFO. This way, I can simply replace my I/O nodes in my FPGA VI with a sub-VI that reads from the DMA FIFO and outputs the various booleans and integers that correspond to their respective I/O lines.

 

This method works, however it runs extremely slow. When running my compiled program on the FPGA and having it interact with the actual camera, it grabs and processes frames at rates in the hundreds of kHz. However, when I run in simulation mode with the data streamed from the TDMS file, it takes a few seconds per frame. This is usacceptable as I need to test the behavior of the program over several "seconds" (which corresponds to hundreds of thousands of frames when the actual FPGA is running the program).

 

My question is, is this to be expected, or am I doing something wrong? By my calculations, the VI that runs fine at a clock rate of 40MHz on the actual FPGA is running at less than 100Hz on the development computer in simulation mode. Has anyone else had experience with the simulated execution mode who can comment on how fast the simulation ran for them?

 

If you'd like to see any of the relevant code, please let me know which parts and I can post screenshots.

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Hi etgohomeok,

 

I believe I understand your explanation, but please correct me if at any point I misread some of the information above.

 

Debugging LabVIEW FPGA code on the host computer definitely has a lot of benefits such as traditional LabVIEW debugging tools, visualization tools, and LabVIEW libraries not usable in LabVIEW FPGA VIs. Most of the time the goal of using the code in simulation mode allows us to verify the proper logic in the VI without the pains of compile time.

 

With that said, execution on a development computer will definitely not run at the rates of your FPGA VI and that can be verified in the Understanding Simulated Time on the Host section of the Debugging FPGA VIs Using Simulation Mode (FPGA Module) help document.

 

When executing the code on the development machine LabVIEW delays as long as necessary to run the logic in the VI rather than making sure it meets the strict timing requirements that compiling the FPGA VI would.

 

I hope this information helps!

 

Sam Burhans
Senior Product Manager
National Instruments
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