A Simulink subsystem was converted into VHDL using HDL Coder. The subsystem runs at frequency of 50 kHz (sampling time), with target frequency of 200 MHz. The VHDL main and supporting codes were imported into the FPGA Target in Labview FPGA and the syntax of the codes was checked successfully. Then a Component-Level IP of these codes was created.
The Inputs and outputs of the Component-Level IP were used inside a while loop of 4000 clock ticks (with 200 MHz clock / 50 kHz sample time = 4000 ticks per loop time).
The VI was then compiled on the FPGA Target, but “Timing error” occurs. The Timing Violation Analysis window says that the requirement of 5 nano seconds was missed by 42.30 nano seconds.
The Simulink model used to generate the HDL code is not complex nor contains any computational operation. And a very equivalent block diagram was implemented on Labview FPGA and was able to be compiled on the FPGA with no problem.
The problem We are having is how to dictate Labview FPGA to have the CLIP operates with a sampling frequency of 50 kHz given that the clock frequency of the FPGA Target is 200 MHz.
