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Labview FPGA Compile Error

Hello there, I'm using Labview 7.1, FPGA Module and the PXI 7831R. My Problem is, that my FPGA vi works properly until I want to compile it. The error Message is:

ERROR:xflow - Program xst returned error code 6. Aborting flow execution...

After playing a little bit with my Program I found out, that this error only occurs if I use the property node with rising or falling edge. I found an example vi called "FPGA SPI Comm" in the Development Zone which has rather the same functions like my vi but the Compiler writes the same error.

Is there anyone who could help me?

thx
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Message 1 of 8
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Could you post your vi or the one you found? I don't recall seeing this
error before, and I do use the wait on edge methods.

"Scheffe" <x@no.email> wrote in message news:181306@exchange.ni.com...
> Hello there, I'm using Labview 7.1, FPGA Module and the PXI 7831R. My
> Problem is, that my FPGA vi works properly until I want to compile it. The
> error Message is:<br><br>ERROR:xflow - Program xst returned error code 6.
> Aborting flow execution...<br><br>After playing a little bit with my
> Program I found out, that this error only occurs if I use the property
> node with rising or falling edge. I found an example vi called "FPGA SPI
> Comm" in the Development Zone which has rather the same functions like my
> vi but the Compiler writes the same error.<br><br>Is there anyone who
> could help me?<br><br>thx


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Message 2 of 8
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thx for your interest !

here are my files...

could it be, that I have to configure the VISA ?
I have no idea how it works with this card, I got
it this week.
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Message 3 of 8
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I replied to this yesterday but I don't see it here. I'll try again from
memory.

I got the same error 6, plus noticed that preceding that message was another
that alluded to an unsupported feature. I suspect that the wait on edge
methods cannot be used on digital outputs. The manual states that the wait
on edge methods can be used on digital inputs and does not mention outputs.

I think that you could use single cycle timed loops to implement the SPI
algorithm. Cycle the clock output on each iteration and then read or write
data according to whether the clock was set high or low.


"Scheffe" <x@no.email> wrote in message news:181622@exchange.ni.com...
> thx for your interest !<br><br>here are my files...<br><br>could it be,
> that I have to configure the VISA ? <br>I have no idea how it works with
> this card, I got <br>it this week.
>
>
> 0010_SPI.zip:
> http://forums.ni.com/attachments/ni/170/105696/1/0010_SPI.zip


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Message 4 of 8
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thx I will try this... until NI sends me the English version of Labview 7.1

The support team told me after some days, thatit is a known bug that the German Labview 7.1 and the English FPGA version produce this error. The bug will be eliminated in the next German Labview version.

But thx a lot for your help !!!
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Message 5 of 8
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Even after the bug is fixed you might what to try a SCTL solution. Using
SCTL's produces smaller code and supposedly reduces jitter. Just remember
that if you use a digital I/O point in an SCTL all references to that point,
including methods, must also be in an SCTL.


"Scheffe" <x@no.email> wrote in message news:182380@exchange.ni.com...
> thx I will try this... until NI sends me the English version of Labview
> 7.1<br><br>The support team told me after some days, thatit is a known bug
> that the German Labview 7.1 and the English FPGA version produce this
> error. The bug will be eliminated in the next German Labview
> version.<br><br>But thx a lot for your help !!!


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Message 6 of 8
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Okay, I will take account of this. But how do I get a clock rate of 8 MHz if I can't set the ticks of the SCTL. Could you give me please a short example how you work with more than one SCTL?
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Message 7 of 8
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> how do I get a clock rate of 8 MHz if I can't set the ticks of the SCTL.

Actually, for 8MHz, using an SCTL isn't needed for its timing benefits but
could still save slices. The example you posted changed every tick, an
application which should use an SCTL.

I would still put the code that reads and writes data in the same frame as
the code that toggles the clock so you don't have to poll for the clock
phase.

>Could you give me please a short example how you work with more than one
>SCTL?

Working with more than one SCTL isn't much different than using multiple
while loops. But there are restrictions on what can go in an SCTL. And, as
I mentioned previously, if you use a digital I/O in an SCTL all other uses
of that same pointname have to be in an SCTL. If you do something that
isn't allowed you'll find out when you try to compile. Unfortunately, as
you've already found out, the error messages don't mean anything to us
users. I've had to guess and re-read the manual several times to work out
compile errors..


Message 8 of 8
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