I am working with the PXIe: 7858r FPGA in labview. I have been able to add CLIPs of VHDL code including ports that contain only input and output types. The below link under the section "Add CLIP to Project" are the steps that I have been following to add CLIPs:
However, when attempting to add a CLIP that contains VHDL port type inout, I receive an error that states: "a port in the top-level synthesis file is of inout type, which is not supported. replace the inout port with two separate ports, in and out". Is there no way to have a CLIP added to a labview project with bidirectional ports? If not, what is a work around that I can try.