LabVIEW <--> FPGA Module <--> Vivado Compilation Compatibility

[CodyDillinger]

Hello,

In this procedure, LabVIEW 2019 / FPGA Module 2019 / Vivado2017 Compilation 2019 are recommended:

HDL Coder™ and LabVIEW FPGA: Importing HDL Coder Exports in LabVIEW FPGA - NI

The PC I am currently using has LabVIEW 2018. Assuming I keep LabVIEW 2018, is compatibility okay to use:

1. LabVIEW 2018 & FPGA Module 2019 & Vivado2017 Compilation 2018?

2. LabVIEW 2018 & FPGA Module 2019 & Vivado2017 Compilation 2019?

3. LabVIEW 2018 & FPGA Module 2018 & Vivado2017 Compilation 2018?

It will be mainly for use with PXI 7868R.

Thank you,

Cody

[Terry_ALE]

You must use the same version of LabVIEW and LabVIEW FPGA.  For LabVIEW 2018, you need LabVIEW FPGA 2018.

For the 7868 you need "LabVIEW 2018 FPGA Module Xilinx Compilation Tool for Vivado 2017.2" (see https://www.ni.com/en-us/support/documentation/compatibility/19/compatibility-between-xilinx-compila...)

[CodyDillinger]

Great, thank you.

On the same topic from the NI source I linked above, for importing HDL to LabVIEW, what is the difference between a single-cycle timed loop and a regular timed loop? There are different help pages for these items with different descriptions (I understand the functional difference where the single cycle one uses the FPGA clock rate), however with the FPGA module installed, clicking "add to block diagram" on the single-cycle timed loop simply adds a regular timed loop. The instructions also say "must use single cycle timed loop for IP integration blocks" but then the image shows only the regular timed loop.

Cody

[Terry_ALE]

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@CodyDillinger wrote:

Great, thank you.

On the same topic from the NI source I linked above, for importing HDL to LabVIEW, what is the difference between a single-cycle timed loop and a regular timed loop? There are different help pages for these items with different descriptions (I understand the functional difference where the single cycle one uses the FPGA clock rate), however with the FPGA module installed, clicking "add to block diagram" on the single-cycle timed loop simply adds a regular timed loop. The instructions also say "must use single cycle timed loop for IP integration blocks" but then the image shows only the regular timed loop.

Cody

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In LabVIEW FPGA a timed loop is a single cycle timed loop.

[Intaris]

The meaning of "single cycle" in "Single cycle timed loop" means that all of the datapaths must compile at the clock rate of the loop. You can break up longer paths by introducing pipelining, but each single clock cycle, each function inputs and outputs once.

This is different to "standard" loops on FPGA where each node can take multiple clocks before it outputs anything and everything is serialised.

It does not mean it only iterates for a single cycle.

[CodyDillinger]

Thanks for the explanation.

I also noticed that the PXIe-7868R help page states "this device supports the single-cycle timed loop for digital I/O only." Does this mean that AIO ports will be entirely unavailable if there is any single cycle timed loop present in any of the FPGA VIs? Or does it simply mean an AIO pin cannot be placed inside of a single cycle timed loop?